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參數(shù)資料
| 型號： | M32000D4BFP-80 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 32 Bits Microcomputer(32位 單片機) |
| 中文描述： | 32位單片微機（32位單片機） |
| 文件頁數(shù)： | 26/44頁 |
| 文件大小： | 448K |
| 代理商： | M32000D4BFP-80 |
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
26
M32000D4BFP-80
(master)
ROM
ASIC
PP0
M/S
M/S
HREQ
INT
M32000D4BFP-80
(slave)
HACK
HREQ
HACK
INT
bus
arbiter
Master/slave mode
The M32000D4BFP-80 has an M/S (master/slave) pin for multipro-
cessor configuration use.
master mode (M/S = "H")
This is normal operation mode. Set the M/S pin to an "H" level. It is
used when the M32000D4BFP-80 is used as the main CPU in a
system.
slave mode (M/S = "L")
This operation mode is for when the M32000D4BFP-80 is used as a
coprocessor. Set the M/S pin to an "L" level. When set to slave mode,
the M32000D4BFP-80 does not start operation even after a reset,
until an interrupt request or the SBI is input. Processing is carried out
by communicating with the master M32000D4BFP-80, using the two
programmable I/O ports and the external interrupt signal.
D24
D25
D26
D27
D28
D29
D30
D31
LM
lock control register (MLCR) < address: H'FFFF FFF7>
Fig. 26 Lock control register
0: HREQ
exclusive
lock mode
___
1: CS exclusive
lock mode
R = 0 ... "0" when reading
W =
... write enabled
R =
W =
... read enabled
: write disabled
<at reset: H'00>
R
0
D
24 - 30
bit name
Not
assigned.
LM
(lock mode)
function
W
31
Coprocessor only configuration example
The slave M32000D4BFP-80 accesses only the internal DRAM and
never the external bus. M/S and HREQ are fixed at the "L" level. The
slave M32000D4BFP-80 executes the instructions that the master
M32000D4BFP-80 downloads to the internal DRAM. The data trans-
fer request (processing complete) from the slave M32000D4BFP-80
is notified to the master M32000D4BFP-80 by inputting the interrupt
request via the programmable I/O port. The data transaction is car-
ried out when the master M32000D4BFP-80 accesses the internal
DRAM in the slave M32000D4BFP-80.
Common bus coprocessor configuration example
In this configuration, the slave M32000D4BFP-80 can also access
the external bus. Communications between the master and slave
CPUs is carried out using the programmable I/O ports and the inter-
rupt request input.
<coprocessor only configuration>
<common bus coprocessor configuration>
Fig. 27 Master/slave system configuration example
M32000D4BFP-80
(master)
ROM
ASIC
INT
PP0
M/S
M/S
HREQ
INT
M32000D4BFP-80
(slave)
no access to
external bus
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