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參數(shù)資料
| 型號： | M32000D4BFP-80 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 32 Bits Microcomputer(32位 單片機) |
| 中文描述： | 32位單片微機（32位單片機） |
| 文件頁數(shù)： | 25/44頁 |
| 文件大?。?/td> | 448K |
| 代理商： | M32000D4BFP-80 |
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
25
("L" output)
("L" output)
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
8
CLKIN
HREQ
BCH, BCL
D0 - D15
DC
R/W
hold shift
hold
return
HACK
A8 - A30
CS
write
write
write
write
Note:
"Hi-Z" means high impedance, and indicates sampling timing.
The value of the R/W signal that controls the data direction of the bus interface
8
cannot be changed during CS="L, 3 to 7 CLKIN clock periods are necessary for writing
writing operations within an 128-bit boundary are completed in 1 CLKIN clock period.
During these wait cycle period, CS cannot be returned to "H" level (the access
cannot be aborted). CS can only be returned to a "H" level after DC is driven to "L".
When the M32000D4BFP-80 is in the hold state and an "L" level is
input to CS, the M32000D4BFP-80 interprets it as a bus access re-
quest to the internal DRAM. In this case, when the R/W signal is at
an "L" level, the memory controller drives a write cycle to the internal
DRAM. Byte data control is specified by the BCH and BCL signals.
Only data in the byte positions for which an "L" level is input to BCH
or BCL are written. When writing is complete, an "L" level DC signal
is output. The M32000D4BFP-80 stores the requested data in the
128-bit data buffer of the BIU, before writing to the internal DRAM.
This reduces the number of accesses to the internal DRAM when a
request to writing to consecutive addresses is made, and improves
bus cycle throughput. Consecutive write cycles within an 128-bit
boundary are completed in 1 CLKIN clock period. 3 to 7 CLKIN clock
periods are necessary for a write access crossing an 128-bit bound-
ary when writing to the internal DRAM. Once the external bus master
write cycle has been driven, it cannot be aborted. When an "L" level
is input to CS and an access has started, the values of this and other
control signals should be held during the wait cycles (that is while DC
= "H"). After DC outputs an "L" level (access complete), return CS to
the "H" level between the CLKIN falling edge corresponding to the
last write cycle and the following CLKIN falling edge. Return HREQ
to the "H" level to return the M32000D4BFP-80 to the normal opera-
tion mode from the hold state either at the same time as or after CS
is returned to the "H" level.
When the external bus master makes an access, the value of the
R/W signal that controls the data direction of the bus interface can-
not be changed during CS="L". Therefore, read cycles and write cycles
cannot be mixed while CS = "L". When starting a write cycle follow-
ing after a read cycle and starting a read cycle following a write cycle,
keep the CS signal at an "H" level for at least 1 CLKIN.
Fig. 24 Write bus cycle to internal DRAM
Fig. 25 Read/write bus cycle to internal DRAM
CLKIN
HREQ
BCH, BCL
D0 - D15
DC
R/W
hold shift
hold
return
HACK
A8 - A30
CS
("L" output)
read
CS = "H"
write
("L" output)
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
"Hi-Z"
8
"Hi-Z"
"Hi-Z"
Note:
"Hi-Z" means high-impedance, and indicates sampling timing.
Also, where marked above with
8
, keep CS signal to "H" at least 1 CLKIN when
starting a write bus cycle after a read bus cycle or a read bus cycle after a write
bus cycle.
"Hi-Z"
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