參數(shù)資料
型號: M13S128324A-5BG
廠商: Electronic Theatre Controls, Inc.
英文描述: Modify typing error of Pin Arrangement
中文描述: 修改輸入錯誤的管腳配置
文件頁數(shù): 8/48頁
文件大?。?/td> 803K
代理商: M13S128324A-5BG
ES MT
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2006
Revision : 1.0 8/48
AC Timing Parameter & Specifications-continued
-5
-6
Parameter
Symbol
min
max
min
max
Unit
Half Clock Period
t
HP
t
CL
min or t
CH
min
-
t
CL
min or t
CH
min
-
ns
DQ-DQS output hold
time
t
QH
t
HP
-0.45
-
t
HP
-0.5
-
ns
ACTIVE to PRECHARGE
command
t
RAS
8
120Kns
7
120Kns
t
CK
Row Cycle Time
t
RC
12
-
10
-
t
CK
AUTO REFRESH Row Cycle
Time
t
RFC
14
-
12
-
t
CK
ACTIVE to READ,WRITE
delay
t
RCD
4
-
3
-
t
CK
PRECHARGE command
period
t
RP
4
-
3
-
t
CK
ACTIVE to READ with
AUTOPRECHARGE
command
t
RAP
4
-
3
-
t
CK
ACTIVE bank A to ACTIVE
bank B command
t
RRD
2
-
2
-
t
CK
Write recovery time
t
WR
15
-
15
-
ns
Write data in to READ
command delay
t
WTR
2
-
2
-
t
CK
Col. Address to Col. Address
delay
t
CCD
1
-
1
-
t
CK
Average periodic refresh
interval
t
REFI
-
7.8
-
7.8
us
Write preamble
t
WPRE
0.25
-
0.25
-
t
CK
Write postamble
t
WPST
0.4
0.6
0.4
0.6
t
CK
DQS read preamble
t
RPRE
0.9
1.1
0.9
1.1
t
CK
DQS read postamble
t
RPST
0.4
0.6
0.4
0.6
t
CK
Clock to DQS write preamble
setup time
t
WPRES
0
-
0
-
ns
Load Mode Register /
Extended Mode register
cycle time
t
MRD
2
-
1
-
t
CK
Exit self refresh to READ
command
t
XSRD
200
-
200
-
t
CK
Exit self refresh to
non-READ command
t
XSNR
75
-
75
-
ns
Autoprecharge write
recovery+Precharge time
t
DAL
(t
WR
/t
CK
)
+
(t
RP
/t
CK
)
-
(t
WR
/t
CK
)
+
(t
RP
/t
CK
)
-
t
CK
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M13S128324A-6BG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S128324A-6BIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM