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參數(shù)資料
| 型號： | M13S128324A-5BG |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Modify typing error of Pin Arrangement |
| 中文描述： | 修改輸入錯誤的管腳配置 |
| 文件頁數(shù)： | 6/48頁 |
| 文件大小： | 803K |
| 代理商： | M13S128324A-5BG |
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ES MT
DC Specifications
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2006
Revision : 1.0 6/48
Parameter
Symbol
Test Condition
Version
Unit Note
-5
-6
-
-
Operation Current
(One Bank Active)
IDD0
t
RC
= t
RC
(min) t
CK
= t
CK
(min)
Active – Precharge
Burst Length = 2 t
RC
= t
RC
(min), CL=
2.5 I
OUT
= 0mA, Active-Read-
Precharge
175
145
mA
-
Operation Current
(One Bank Active)
IDD1
190
180
mA
-
Precharge Power-down Standby
Current
IDD2P
CKE
≤
V
IL
(max), t
CK
= t
CK
(min), All
banks idle
40
40
mA
-
Idle Standby Current
IDD2N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CK
=
t
CK
(min)
115
95
mA
-
Active
Current
Power-down
Standby
IDD3P
All banks ACT, CKE
≤
V
IL
(max), t
CK
=
t
CK
(min)
50
45
mA
-
Active Standby Current
IDD3N
One bank; Active-Precharge, t
RC
=
t
RAS
(max),
t
CK
= t
CK
(min)
120
110
mA
-
Operation Current (Read)
IDD4R
Burst Length = 2, CL= 2.5 , t
CK
= t
CK
(min), I
OUT
= 0Ma
350
300
mA
-
Operation Current (Write)
IDD4W
Burst Length = 2, CL= 2.5 , t
CK
= t
CK
(min)
380
330
mA
-
Auto Refresh Current
IDD5
t
RC
≥
t
RFC
(min)
270
250
mA
-
Self Refresh Current
IDD6
CKE
≤
0.2V
3
3
mA
1
Note 1. Enable on-chip refresh and address counters.
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
V
IH
(AC)
V
REF
+ 0.35
-
V
-
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
V
IL
(AC)
-
V
REF
- 0.35
V
-
Input Different Voltage, CLK and CLK inputs
V
ID
(AC)
0.7
V
DDQ
+0.6
V
1
Input Crossing Point Voltage, CLK and CLK inputs
V
IX
(AC)
0.5*V
DDQ
-0.2
0.5*V
DDQ
+0.2
V
2
Note1. V
ID
is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the
same.
Input / Output Capacitance
(V
DD
= 2.375V~2.75V, V
DDQ
=2.375V~2.75V, T
A
= 25° , f = 1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance
(A0~A11, BA0~BA1, CKE, CS , RAS , CAS ,
WE
)
C
IN1
1
4
pF
Input capacitance (CLK, CLK )
C
IN2
1
5
pF
Data & DQS input/output capacitance
C
OUT
1
6.5
pF
Input capacitance (DM)
C
IN3
1
6.5
pF
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| M13S128324A-5BIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128324A-5LG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128324A-5LIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128324A-6BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128324A-6BIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM |
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