參數(shù)資料
型號(hào)： M13S128324A-5BG
廠商： Electronic Theatre Controls, Inc.
英文描述： Modify typing error of Pin Arrangement
中文描述： 修改輸入錯(cuò)誤的管腳配置
文件頁(yè)數(shù)： 15/48頁(yè)
文件大?。?/td> 803K
代理商： M13S128324A-5BG
ES MT
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2006
Revision : 1.0 15/48
Row Active
The Bank Activation command is issued by holding CAS and
WE
high with CS and RAS low at the rising edge of the
clock (CLK). The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank
Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (t
RCD
min).
Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank.
The minimum time interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank
delay time (t
RRD
min).
Bank Activation Command Cycle (
CAS
Latency = 3)
Read Bank
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by
activating CS , CAS , and deasserting
WE
at the same clock sampling (rising) edge as described in the command truth table.
The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.
Write Bank
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by
activating CS , CAS , and
WE
at the same clock sampling (rising) edge as describe in the command truth table. The length of
the burst will be determined by the values programmed during the MRS command.
A d dr es s
0
1
2
C o m m a n d
B a n k A
Ro w Ad d r .
B a n k A
Co l . A d d r .
RBank A
B a n k B
Ro w Ad d r .
B a n k A
N O P
W r i t e A
wi t h Au t o
B a n k B
A c t i v a t e
N O P
B a n k A
A c t i v a t e
R A S - C A S d e l a y (
t
R C D
)
R A S - R A S d e l a y (
t
R R D
)
R O W C y c l e T i m e (
t
R C
)
: Don't Care
C L K
C L K
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M13S128324A-5BIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S128324A-5LG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S128324A-5LIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S128324A-6BG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S128324A-6BIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
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