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參數(shù)資料
| 型號： | LU3X54FTL |
| 廠商： | Lineage Power |
| 英文描述： | Quad-FET for 10Base-T/100Base-TX/FX(應用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
| 中文描述： | 四為10Base-T/100Base-TX/FX場效應晶體管（應用于10基數(shù)- T的和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 38/52頁 |
| 文件大?。?/td> | 669K |
| 代理商： | LU3X54FTL |
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LU3X54FTL
QUAD-FET for 10Base-T/100Base-TX/FX
Data Sheet
July 2000
38
Lucent Technologies Inc.
MII Station Management
(continued)
Table 21. MR30—Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions
1. Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2 R = read, W = write.
Register/Bit
1
30.15:7 (R28[15:7])
30.6 (CLK_SEL)
Type
2
R/W
R/W
Description
Unused.
Read as 0.
20 MHz Clock Select
.
When this bit is a 1, it enables the two-clock input mode
(20 MHz and 25 MHz). When this bit is a 0, it enables the single-clock input
mode 25 MHz (with 20 MHz clock internally generated). Default state is 0
.
Heartbeat Enable.
When this bit is a 1, the heartbeat function will be
enabled. Valid in 10 Mbits/s mode only. Default state is 0.
Extended Line Length Enable.
When this bit is a 1, the receive squelch
levels are reduced from a nominal 435 mV to 350 mV, allowing reception of
signals with a lower amplitude. Valid in 10 Mbits/s mode only. Default state is
0.
Autopolarity Function Disable.
When this bit is a 0 and the LU3X54FTL is in
10 Mbits/s mode, the autopolarity function will determine if the TP link is wired
with a polarity reversal.
30.5 (HBT_EN)
R/W
30.4 (ELL_EN)
R/W
30.3 (APF_DIS)
R/W
If there is a polarity reversal, the LU3X54FTL will assert the APS bit (register
28, bit 6) and correct the polarity reversal. If this bit is a 1 and the device is in
10 Mbits/s mode, the reversal will not be corrected. Default state is 0.
Reference Select.
When this bit is a 1, the external 10 MHz reference input
clock REF10 is used for phase alignment. Default state is 0.
Serial Select.
When this bit is set to a 1, 10 Mbits/s serial mode will be
selected. When the LU3X54FTL is in 100 Mbits/s mode, this bit will be
ignored. This bit is ORed with the H_DUPLED[C] pin during powerup and
reset. Default state is 0.
No Link Pulse Mode.
Setting this bit to a 1 will allow 10 Mbits/s operation
with link pulses disabled. If the LU3X54FTL is configured for 100 Mbits/s oper-
ation, setting this bit will not affect operation. This bit is ORed with the
LINKLED[A] pin during powerup and reset. Default state is 0.
30.2 (REF_SEL)
R/W
30.1 (SERIAL _SEL)
R/W
30.0 (ENA_NO_LP)
R/W
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