- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384634 > LU3X54FTL (Lineage Power) Quad-FET for 10Base-T/100Base-TX/FX(應用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) PDF資料下載
參數(shù)資料
| 型號： | LU3X54FTL |
| 廠商： | Lineage Power |
| 英文描述： | Quad-FET for 10Base-T/100Base-TX/FX(應用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
| 中文描述： | 四為10Base-T/100Base-TX/FX場效應晶體管（應用于10基數(shù)- T的和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 31/52頁 |
| 文件大?。?/td> | 669K |
| 代理商： | LU3X54FTL |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
Lucent Technologies Inc.
31
Data Sheet
July 2000
LU3X54FTL
QUAD-FET for 10Base-T/100Base-TX/FX
MII Station Management
(continued)
This section provides a detailed discussion of each management register and its bit definitions.
Table 11. MR0—Control Register Bit Descriptions
1. Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read, W = write, NA = not applicable.
Register/Bit
1
0.15 (SW_RESET)
Type
2
R/W
Description
Reset.
Setting this bit to a 1 will reset the entire (all 4 ports, even when only 1
port is addressed) LU3X54FTL. All registers will be set to their default state.
This bit is self-clearing. The default is 0.
Loopback.
When this bit is set to 1, no data transmission will take place on
the media. Any receive data will be ignored. The loopback signal path will con-
tain all circuitry up to but not including the PMD. The default value is a 0.
Speed Selection.
The value of this bit reflects the current speed of operation
(1 = 100 Mbits/s, 0 = 10 Mbits/s). This bit will only affect operating speed when
the autonegotiation enable bit (register 0, bit 12) is disabled (0). This bit is
ignored when autonegotiation is enabled (register 0, bit 12). This bit is ANDed
with the SPEEDLED[D] pin during powerup and reset. The default state is a 1.
Autonegotiation Enable.
The autonegotiation process will be enabled by set-
ting this bit to a 1. The default state is a 1.
Powerdown.
The LU3X54FTL may be placed in a low-power state by setting
this bit to a 1, both the 10 Mbits/s transceiver and the 100 Mbits/s transceiver
will be powered down. While in the powerdown state, the LU3X54FTL will
respond to management transactions. The default state is a 0.
Isolate Mode.
When this bit is set to a 1, the MII outputs will be brought to the
high-impedance state. The default state is a 0. This bit is ORed with the
SPEEDLED[A]/ISOLATE_MODE pin during powerup and reset.
Restart Autonegotiation.
Normally, the autonegotiation process is started at
powerup. The process may be restarted by setting this bit to a 1. The default
state is a 0. The NWAYDONE bit (register 1, bit 5) is reset when this bit goes
to a 1. This bit is self-cleared when autonegotiation restarts.
Duplex Mode.
This bit reflects the mode of operation (1 = full duplex, 0 = half
duplex). This bit is ignored when the autonegotiation enable bit (register 0,
bit 12) is enabled. The default state is a 0. This bit is ORed with the
H_DUPLED[D] pin during powerup or reset.
Collision Test.
When this bit is set to a 1, the LU3X54FTL will assert the COL
signal in response to TX_EN. This bit should only be set when in loopback
mode.
Reserved.
All bits will read 0.
0.14 (LOOPBACK)
R/W
0.13 (SPEED100)
R/W
0.12 (NWAY_ENA)
R/W
0.11 (PWRDN)
R/W
0.10 (ISOLATE)
R/W
0.9 (REDONWAY)
R/W
0.8 (FULL_DUP)
R/W
0.7 (COLTST)
R/W
0.6:0 (RESERVED)
NA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU5X31F | Gigabit Ethernet Transceiver(千兆位以太網(wǎng)收發(fā)器) |
| LUC4AB01 | ATM Buffer Manager (ABM)(ATM緩沖管理器 (ABM)) |
| LUC4AC01 | ATM Crossbar Element (ACE)(ATM縱橫元件（ACE）) |
| LUC4AS01 | ATM Switch Element (ASX)(ATM開關(guān)元件) |
| LUC4AU01 | ATM Layer UNI Manager (ALM)(ATM 層UNI管理器(ALM)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
| LU3X54FTL-HS208-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208-DB | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208-DB |
| LU400 | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:NEMA Cabinet Legs |
| LU400/D | 制造商:OSRAM 功能描述:400W MOGUL BASED GENERAL LIGHTING HIGH PRESSURE SODIUM LAMP, COATED, DAYLIGHT, U |
發(fā)布緊急采購，3分鐘左右您將得到回復。