參數(shù)資料
型號(hào)： LU3X54FTL
廠商： Lineage Power
英文描述： Quad-FET for 10Base-T/100Base-TX/FX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器)
中文描述： 四為10Base-T/100Base-TX/FX場(chǎng)效應(yīng)晶體管（應(yīng)用于10基數(shù)- T的和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器）
文件頁(yè)數(shù)： 2/52頁(yè)
文件大?。?/td> 669K
代理商： LU3X54FTL
Table of Contents
Contents
Page
LU3X54FTL
QUAD-FET for 10Base-T/100Base-TX/FX
Data Sheet
July 2000
2
Lucent Technologies Inc.
Introduction................................................................................................................................................................1
Configuration...........................................................................................................................................................1
Features ....................................................................................................................................................................1
10 Mbits/s Transceiver ............................................................................................................................................1
100 Mbits/s TX Transceiver.....................................................................................................................................1
100 Mbits/s FX Transceiver.....................................................................................................................................1
General ...................................................................................................................................................................4
Description ................................................................................................................................................................4
Bused MII Mode......................................................................................................................................................4
Clocking ..................................................................................................................................................................5
FX Mode .................................................................................................................................................................6
Functional Block Diagrams .....................................................................................................................................7
Application Diagrams..............................................................................................................................................9
Block Diagrams.....................................................................................................................................................11
Pin Information ........................................................................................................................................................13
Pin Diagram for Normal MII Mode.........................................................................................................................13
Pin Diagram for Bused MII Mode..........................................................................................................................14
Pin Maps...............................................................................................................................................................15
Pin Descriptions....................................................................................................................................................16
MII Station Management .........................................................................................................................................29
Basic Operations...................................................................................................................................................29
MII Management Frames......................................................................................................................................29
Management Registers (MR)................................................................................................................................30
Unmanaged Operations........................................................................................................................................40
Mode Select..........................................................................................................................................................40
Absolute Maximum Ratings (TA = 25
°
C)................................................................................................................41
Electrical Characteristics.........................................................................................................................................41
Timing Characteristics (Preliminary) .......................................................................................................................42
Outline Diagram.......................................................................................................................................................51
208-Pin SQFP.......................................................................................................................................................51
Ordering Information................................................................................................................................................52
Tables
Page
Table 1. LU3X54FTL Crystal Specifications ............................................................................................................ 6
Table 2. LU3X54FTL Pin Maps.............................................................................................................................. 15
Table 3. MII/Serial Interface Pins in Normal MII Mode (Four Separate MII Ports)................................................. 16
Table 4. MII/Serial Interface Pins in Bused MII Mode............................................................................................ 18
Table 5. MII Management Pins.............................................................................................................................. 22
Table 6. 10/100 Mbits/s Twisted-Pair (TP) Interface Pins....................................................................................... 22
Table 7. Miscellaneous Pins .................................................................................................................................. 23
Table 8. MII Management Frame Format............................................................................................................... 29
Table 9. MII Management Frames Field Descriptions............................................................................................ 29
Table 10. MII Management Registers (MR)........................................................................................................... 30
Table 11. MR0—Control Register Bit Descriptions................................................................................................ 31
Table 12. MR1—Status Register Bit Descriptions ................................................................................................. 32
Table 13. MR2, 3—PHY Identifier Registers (1 and 2) Bit Descriptions................................................................ 33
Table 14. MR4—Autonegotiation Advertisement Register Bit Descriptions........................................................... 33
Table 15. MR5—Autonegotiation Link Partner (LP) Ability Register (Base Page) Bit Descriptions....................... 34
Table 16. MR5—Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Descriptions........................ 34
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