參數資料
型號： LU3X54FTL
廠商： Lineage Power
英文描述： Quad-FET for 10Base-T/100Base-TX/FX(應用于10基數-T和100基數-TX/FX的四快速以太網收發(fā)器)
中文描述： 四為10Base-T/100Base-TX/FX場效應晶體管（應用于10基數- T的和100基數-TX/FX的四快速以太網收發(fā)器）
文件頁數： 33/52頁
文件大小： 669K
代理商： LU3X54FTL
Lucent Technologies Inc.
33
Data Sheet
July 2000
LU3X54FTL
QUAD-FET for 10Base-T/100Base-TX/FX
MII Station Management
(continued)
Table 13. MR2, 3—PHY Identifier Registers (1 and 2) Bit Descriptions
1. Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read.
Table 14. MR4—Autonegotiation Advertisement Register Bit Descriptions
1. Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read, W = write, NA = not applicable.
Register/Bit
1
2.15:0 (OUI[3:18])
Type
2
R
Description
Organizationally Unique Identifier.
The third through the twenty-fourth bit
of the OUI assigned to the PHY manufacturer by the IEEEare to be placed
in bits [2.15:0] and [3.15:10]. The value for bits 15:0 is 0180h.
Organizationally Unique Identifier.
The remaining 6 bits of the OUI. The
value for bits 15:10 is 1Dh.
Model Number.
6-bit model number of the device. The model number is
54 DEC.
Revision Number.
The value of the present revision number. The value is
01h for the first version.
3.15:10 (OUI[19:24])
R
3.9:4 (MODEL[5:0])
R
3.3:0 (VERSION[3:0])
R
Register/Bit
1
Type
2
Description
4.15 (NEXT_PAGE)
R/W
Next Page.
The next-page function is activated by setting this bit to a 1.
This will allow the exchange of additional data. Data is carried by optional
next pages of information.
Acknowledge.
This bit is the acknowledge bit from the link code word.
Remote Fault.
When set to 1, the LU3X54FTL indicates to the link partner
a remote fault condition.
Reserved.
These bits will read 0.
Pause.
When set to a 1, it indicates that the LU3X54FTL wishes to
exchange flow control information with its link partner.
100Base-T4.
This bit should always be set to 0.
100Base-TX Full Duplex.
If written to 1, autonegotiation will advertise that
the LU3X54FTL is capable of 100Base-TX full-duplex operation.
100Base-TX.
If written to 1, autonegotiation will advertise that the
LU3X54FTL is capable of 100Base-TX operation.
10Base-T Full Duplex.
If written to 1, autonegotiation will advertise that
the LU3X54FTL is capable of 10Base-T full-duplex operation.
10Base-T.
If written to 1, autonegotiation will advertise that the
LU3X54FTL is capable of 10Base-T operation.
Selector Field
. Reset with the value 00001 for IEEE802.3.
4.14 (ACK)
4.13 (REM_FAULT)
R/W
R/W
4.12:11 (RESERVED)
4.10 (PAUSE)
NA
R/W
4.9 (100BASET4)
4.8 (100BASET_FD)
R/W
R/W
4.7 (100BASETX)
R/W
4.6 (10BASET_FD)
R/W
4.5 (10BASET)
R/W
4.4:0 (SELECT)
R/W
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