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參數(shù)資料
| 型號： | LTC3554EPD#TRPB |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.5 A BATTERY CHARGE CONTROLLER, 1295 kHz SWITCHING FREQ-MAX, PQCC20 |
| 封裝： | 3 X 3 MM, 0.55 MM HEIGHT, LEAD FREE, PLASTIC, UTQFN-20 |
| 文件頁數(shù)： | 24/36頁 |
| 文件大?。?/td> | 418K |
| 代理商： | LTC3554EPD#TRPB |
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LTC3554
30
3554p
Holding ON low through the one second power-down
period will not cause a power-up event at end of the one
second period. The ON pin must be brought high following
the power-down event and then go low again to establish
a valid power-up event.
UVLO Minimum Off-Time Timing (Low Battery)
Figure 11 assumes the battery is either missing or at a
voltage below the VOUT UVLO threshold, and the applica-
tion is running via external power (VBUS). A glitch on the
external supply causes VOUT to drop below the VOUT UVLO
threshold temporarily. This VOUT UVLO condition causes
the pushbutton circuitry to transition from the PON state
to the PDN2 state. Upon entering the PDN2 state PGOOD
will go low and the bucks power down together. If the
external supply recovers after entering the PDN2 state
such that VOUT is no longer in UVLO, then the LTC3554
will transition back into the PUP2 state once the PDN2 one
second delay is complete. Following the state diagram, the
transition from PDN2 to PUP2 in this case actually occurs
via a brief visit to the POFF state, during which the state
machine immediately recognizes that valid external power
is available and transitions into the PUP2 state. Entering
the PUP2 state will cause the bucks to sequence up as
described previously in the power-up sections.
Note: If VOUT drops too low (about TBDV) the LTC3554
will see this as a POR condition and will enter PDN1 rather
than PDN2 state. One second later the part will transition
to the HR state. Under these conditions the part may or
may not power-up after entering the HR state.
Hard Reset Timing
HARD RESET provides an ultralow power-down state for
shipping or long term storage as well as a way to power
down the application in case of a software lockup. In the
case of software lockup, the user can hold the pushbutton
(ON low) for 5 seconds and a hard reset event (HRST) will
OPERATION
BAT
VBUS
ON (PB)
PBSTAT
BUCK1
BUCK2
PGOOD
PWR_ON1
PWR_ON2
STATE
PON
PUP2
PDN2
3554 TD05
5s
1s, BUCK1 POWERS UP
BUCK2 POWERS UP
230ms
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Figure 11. UVLO Minimum Off-Time Timing
BAT
VBUS
ON (PB)
PBSTAT
BUCK1
BUCK2
PGOOD
PWR_ON1
PWR_ON2
STATE
PON
HR
PDN1
3554 TD06
BUCK 2
400ms
BUCK 1
50ms
5s
1s
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Figure 12. Hard Reset Via Holding ON Low for 5s
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