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參數(shù)資料
| 型號(hào)： | LMX3305SLBX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Triple Phase Locked Loop for RF Personal Communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2300 MHz, QCC24 |
| 封裝： | CSP-24 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 213K |
| 代理商： | LMX3305SLBX |
1.0 Functional Description
(Continued)
1.9 MICROWIRE INTERFACE
The programmable register set is accessed through the mi-
crowire serial interface. The interface is comprised of three
signal pins: Clock, Data, and LE.After the LE goes LOW, se-
rial data is clocked into the 32-bit shift register upon the ris-
ing edge of Clock MSB first. The last three data bits shifted
into the shift register select one of five addresses. When LE
goes HIGH, data is transferred from the shift registers into
one of the four register bank latches. Selecting the address
<
000
>
presets the data in the four register banks. The syn-
thesizer can be programmed even in the power down (or not
enabled) state.
1.10 LOCK DETECT OUTPUTS
The open-drain Lock Detect is available in the LMX3305 to
provide a digital or analog lock detect indication for the sum
of the active PLLs. In the digital lock detect mode, an internal
digital filter produces a logic level HIGH at the lock detect
output when the error between the phase detector inputs is
less than 15 ns for five consecutive comparison cycles. The
lock detect output is LOW when the error between the phase
detector inputs is more than 30 ns for one comparison cycle.
In the analog lock detect mode, the lock detect pin becomes
active low whenever any of the active PLLs are charge
pumping. The
Lock_Det
pin can also be programmed to
provide the outputs of the R, N or fastlock timeout counters.
1.11 POWER CONTROL
Each PLL is individually power controlled by the microwire
power down bits
Rx_PWDN
,
Tx_PWDN
and
RF_PWDN
. Al-
ternatively, the PLLs can also be power controlled by the
Tx_En, Rx_En,
and
RF_En
pins. The enable pins override
the power down bits except for the
V2X
bit. When the re-
spective PLL’s enable pin is high, the power down bits deter-
mine the state of power control. Activation of any PLL power
down modes result in the disabling of the respective N
counter and de-biasing of its respective f
input (to a high
impedance state). The R counter functionality also becomes
disabled when the power down bit is activated. The refer-
ence oscillator block powers down and the
OSC
pin reverts
to a high impedance state when all of the enable pins are
LOW or all of the power down bits are programmed HIGH,
unless
V2X
bit is HIGH. Power down forces the respective
charge pump and phase comparator logic to a TRI-STATE
condition.Apower down counter reset function resets both N
and R counters of the respective PLL. Upon powering up the
N counter resumes counting in “close” alignment with the R
counter (the maximum error is one prescaler cycle). The mi-
crowire control register remains active and capable of load-
ing and latching in data during all of the power down modes.
L
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