參數(shù)資料
型號: LMX3305SLBX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: Triple Phase Locked Loop for RF Personal Communications
中文描述: PLL FREQUENCY SYNTHESIZER, 2300 MHz, QCC24
封裝: CSP-24
文件頁數(shù): 19/24頁
文件大?。?/td> 213K
代理商: LMX3305SLBX
2.0 Programming Description
(Continued)
2.5.5 RF_Icpo (RF_R[4]-[3])
These two bits set the charge pump gain of the RF PLL. The user is able to set the charge pump gain during the acquisition phase
of the fastlock mode to 4X, 7X or 9X.
Charge Pump
Gain
100 μA
400 μA
700 μA
900 μA
RF_R[4]
RF_R[3]
0
0
1
1
0
1
0
1
2.5.6 RF_PD_POL (RF_R[2])
This bit sets the polarity of the RF phase detector. It is set to one when RF VCO characteristics are positive. When RF VCO fre-
quency decreases with increasing control voltage, RF_PD_POL should be set to zero.
2.5.7 RF_RST (RF_R[1])
This bit will reset the RF R and N counters when it is set to one. For normal operation, RF_RST should be set to zero.
2.5.8 V2X (RF_R[0])
V2X when set high enables the voltage doubler for the RF charge pump supply.
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