參數(shù)資料
型號(hào)： LMX3305SLBX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： Triple Phase Locked Loop for RF Personal Communications
中文描述： PLL FREQUENCY SYNTHESIZER, 2300 MHz, QCC24
封裝： CSP-24
文件頁(yè)數(shù)： 22/24頁(yè)
文件大小： 213K
代理商： LMX3305SLBX
2.0 Programming Description
(Continued)
2.6.3 FRAC_D (RF_N[9]-[6])
These four bits, the fractional accumulator modulus denominator, set the fractional denominator from 1/2 to 1/16 resolution.
Modulus Denominator
1-8
9
10-14
15
16
FRAC_D [3:0]
Not Allowed
1
1
0
0
1
0
0
1
0
1
1
0
MODULUS NUMERATOR (FRAC_N) AND DENOMINATOR (FRAC_D) PROGRAMMING
Fractional
Numerator
(FRAC_N)
RF_N[13]-[10]
Fractional Denominator, (FRAC_D)
RF_N[9]-[6]
7
8
0110
0111
1000
Functions like an integer-N PLL as fractional component is set to 0.
1
2
3
4
5
6
9
10
11
12
13
14
15
16
0000
0001
0010
0011
0100
0101
1001
1010
1011
1100
1101
1110
1111
0=0000
1=0001
2=0010
3=0011
4=0100
5=0101
6=0110
7=0111
8=1000
9=1001
10=1010
11=1011
12=1100
13=1101
14=1110
15=1111
*
(8/16)
*
(5/15)
*
(4/16)
*
(3/15)
*
(2/12)
*
(2/14)
*
(2/16)
1/9
2/9
3/9
4/9
5/9
6/9
7/9
8/9
1/10
2/10
3/10
4/10
5/10
6/10
7/10
8/10
9/10
1/11
2/11
3/11
4/11
5/11
6/11
7/11
8/11
9/11
10/11
1/12
2/12
3/12
4/12
5/12
6/12
7/12
8/12
9/12
10/12
11/12
1/13
2/13
3/13
4/13
5/13
6/13
7/13
8/13
9/13
10/13
11/13
12/13
1/14
2/14
3/14
4/14
5/14
6/14
7/14
8/14
9/14
10/14
11/14
12/14
13/14
1/15
2/15
3/15
4/15
5/15
6/15
7/15
8/15
9/15
10/15
11/15
12/15
13/15
14/15
1/16
2/16
3/16
4/16
5/16
6/16
7/16
8/16
9/16
10/16
11/16
12/16
13/16
14/16
15/16
*
(10/15)
*
(8/16)
*
(6/15)
*
(4/12)
*
(4/14)
*
(4/16)
*
(12/16)
*
(9/15)
*
(6/12)
*
(6/14)
*
(6/16)
*
(12/15)
*
(8/12)
*
(8/14)
*
(8/16)
*
(10/12)
*
(10/14)
*
(10/16)
*
(12/14)
*
(12/16)
*
(14/16)
FRAC_D values between 1 to 8 are not allowed.
Remark:
The
*
(FRAC_N / FRAC_D) denotes that the fraction number can be represented by (FRAC_N / FRAC_D) as indicated in the parenthesis. For example,
1/2 can be represented by 8/16.
2.6.4 FBPS (RF_N[5])
This bit when set to one will bypass the delay line calculation used in the fractional circuitry. This will improve the phase noise
while sacrificing performance on reference spurs. When the bit is set to zero, the delay line circuit is in effect to reduce reference
spur.
2.6.5 PCS (RF_N[4])
This bit will determine whether the RF PLL should operate in PCS frequency range or cellular frequency range. When the bit is
set to one, the RF PLL will operate in the PCS mode and when it is set to zero, the cellular mode.
2.6.6 RF_PWDN (RF_N[3])
This bit will asynchronously powerdown the RF PLL when set to one. For normal operation, it should be set to zero.
2.6.7 Test (RF_N[2]-[0])
These bits are the internal factory testing only. They should be set to zero for normal operation.
L
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