參數(shù)資料
型號(hào)： LMX3305SLBX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： Triple Phase Locked Loop for RF Personal Communications
中文描述： PLL FREQUENCY SYNTHESIZER, 2300 MHz, QCC24
封裝： CSP-24
文件頁(yè)數(shù)： 21/24頁(yè)
文件大?。?/td> 213K
代理商： LMX3305SLBX
2.0 Programming Description
(Continued)
2.6.1 RF_N_CNTR (RF_N[28]-[14])
The RF N counter value is determined by three counter values that work in conjunction with four prescalers. This quadruple
modulus prescaler architecture allows lower minimum continuous divide ratios than are possible with a dual modulus prescaler
architecture. For the determination of the A, B, and C counter values, the fundamental relationships are shown below.
N = PC + 4B + A
C
≥
max {A,B} + 2
The A, B, and C values can be determined as follows:
C = N
div
P
B = (N - CP)
div
4
A = (N - CP)
mod
4
N REGISTER FOR THE CELLULAR (8/9/12/13) PRESCALER OPERATING IN FRACTIONAL MODE
Divide
Ratio
1-23
24-39
40
41
…
16383
RF_N_CNTR [14:0]
C Word
B Word
A Word
Divide Ratios Less than 24 are impossible since it is required that C
≥
3
Some of these N values are Legal Divide Ratios, some are not
0
0
0
0
0
0
0
0
0
0
.
.
.
.
.
1
1
1
1
1
0
0
.
1
0
0
.
1
0
0
.
1
1
1
.
1
0
0
.
1
1
1
.
1
0
0
0
0
0
0
.
1
0
0
.
1
0
1
.
1
N REGISTER FOR THE PCS (16/17/20/21) PRESCALER OPERATING IN FRACTIONAL MODE
Divide
Ratio
1-47
48-79
80
81
…
32767
RF_N_CNTR [14:0]
C Word
B Word
A Word
Divide Ratios Less than 48 are impossible since it is required that C
≥
3
Some of these N values are Legal Divide Ratios, some are not
0
0
0
0
0
0
0
0
0
0
.
.
.
.
.
1
1
1
1
1
0
0
.
1
0
0
.
1
0
0
.
1
1
1
.
1
0
0
.
1
1
1
.
1
0
0
0
1
0
0
.
1
0
0
.
1
0
1
.
1
2.6.2 FRAC_N (RF_N[13]-[10])
These four bits, the fractional accumulator modulus numerator, set the fractional numerator values in the fraction.
Modulus Numerator
0
1
2
14
15
FRAC_N [3:0]
0
0
0
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
0
1
L
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