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參數(shù)資料
| 型號： | LMX3305SLBX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Triple Phase Locked Loop for RF Personal Communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2300 MHz, QCC24 |
| 封裝： | CSP-24 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 213K |
| 代理商： | LMX3305SLBX |
Pin Descriptions
Pin No.
1
Pin Name
RF_CP
o
I/O
O
Description
Charge pump output for RF PLL. For connection to a loop filter for driving the input of
an external VCO.
RF PLL ground.
RF prescaler input. Small signal input from the RF Cellular or PCS VCO.
RF PLL power supply voltage. Input may range from 2.7V to 3.6V. Bypass capacitors
should be placed as close as possible to this pin and be connected directly to the
ground plane. Tx V
CC
= Rx V
CC
= RF V
CC
.
Multiplexed output of the RF, Rx, and Tx PLL’s analog or digital lock detects. The
outputs from the R, N and Fastlock counters can also be selected for test purposes.
Refer to Section 2.3.4 for more detail.
No Connect.
RF PLL enable pin. A LOW on RF En powers down the RF PLL and TRI-STATE
s the
RF PLL charge pump.
Rx PLL enable pin. A LOW on Rx En powers down the Rx PLL and TRI-STATEs the
Rx PLL charge pump.
Tx PLL enable pin. A LOW on Tx En powers down the Tx PLL and TRI-STATEs the
Tx PLL charge pump.
High impedance CMOS clock input. Data for the various counters is clocked on the
rising edge into the CMOS input.
Binary serial data input. Data entered MSB first.
High impedance CMOS input. When LE goes LOW, data is transferred into the shift
registers. When LE goes HIGH, data is transferred from the internal registers into the
appropriate latches.
Tx prescaler input. Small signal input from the Tx VCO.
Charge pump output for Tx PLL. For connection to a loop filter for driving the input of
an external VCO.
Tx PLL ground.
Tx PLL power supply voltage input. Input may range from 2.7V to 3.6V. Bypass
capacitors should be placed as close as possible to this pin and be connected directly
to the ground plane. Tx V
CC
= Rx V
CC
= RF V
CC
.
PLL reference input which has a V
CC
/2 input threshold and can be driven from an
external CMOS or TLL logic gate. The R counter is clocked on the falling edge of the
OSC
IN
signal.
Rx PLL power supply voltage. Input ranges from 2.7V to 3.6V. Bypass capacitors
should be placed as close as possible to this pin and be connected directly to the
ground plane. Tx V
CC
= Rx V
CC
= RF V
CC
.
Rx PLL ground.
Charge pump output for Rx PLL. For connection to a loop filter for driving the input of
an external VCO.
Rx prescaler input. Small signal input from the Rx VCO.
An open drain NMOS output which can be use for bandswitching or Fastlocking the
RF PLL. (During Fastlock mode a second loop filter damping resistor can be switched
in parallel with the first to ground.) Refer to Section 2.5.3 for more detail.
An open drain NMOS output which can be use for bandswitching or Fastlocking the
RF PLL. (During Fastlock mode a second loop filter damping resistor can be switched
in parallel with the first to ground.) Refer to Section 2.5.3 for more detail.
RF PLL charge pump power supply. An internal voltage doubler can be enabled in 3V
applications to allow the RF charge pump to operate over a wider tuning range.
2
3
4
RF_GND
RF_F
IN
RF_V
CC
PWR
I
PWR
5
Lock_Det
O
6
7
N/C
RF_En
I
8
Rx_En
I
9
Tx_En
I
10
Clock
I
11
12
Data
LE
I
I
13
14
Tx_F
IN
Tx_CP
o
I
O
15
16
Tx_GND
Tx_V
CC
PWR
17
OSC
IN
I
18
Rx_V
CC
PWR
19
20
Rx_GND
Rx_CP
o
PWR
O
21
22
Rx_F
IN
RF_Sw1
I
O
23
RF_Sw2
O
24
V
P
O
L
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