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參數(shù)資料
| 型號： | LMX3305SLBX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Triple Phase Locked Loop for RF Personal Communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2300 MHz, QCC24 |
| 封裝： | CSP-24 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 213K |
| 代理商： | LMX3305SLBX |
2.0 Programming Description
(Continued)
Typical Lock Detect Timing
2.3.5 Rx_PD_POL (IF_R[2])
This bit sets the polarity of the Rx phase detector. It is set to one when Rx VCO characteristics are positive. When Rx VCO fre-
quency decreases with increasing control voltage, Rx_PD_POL should set to zero.
2.3.6 Rx_RST (IF_R[1])
This bit will reset the Rx R and N counters when it is set to one. For normal operation, Rx_RST should be set to zero.
DS101361-6
L
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