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參數(shù)資料
| 型號： | LMX3305SLBX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Triple Phase Locked Loop for RF Personal Communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2300 MHz, QCC24 |
| 封裝： | CSP-24 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大小： | 213K |
| 代理商： | LMX3305SLBX |
2.0 Programming Description
(Continued)
2.3.1 10-Bit IF Programming Reference Divider Ratio (Tx R Counter, Rx R Counter)
Divide Ratio
2
3
1023
Tx_R_CNTR [9:0] or Rx_R_CNTR [9:0]
0
0
0
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
0
1
1
Note:
Divide ratio for both Tx and Rx R counters are from 2 to 1023.
2.3.2 Tx_PD_POL (IF_R[18])
This bit sets the polarity of the Tx phase detector. It is set to one when Tx VCO characteristics are positive. When Tx VCO fre-
quency decreases with increasing control voltage, Tx_PD_POL should be set to zero.
2.3.3 Tx_RST (IF_R[17])
This bit will reset the Tx R and N counters when it is set to one. For normal operation, Tx_RST should be set to zero.
2.3.4 LD (IF_R[16]-[13])
The LD pin is a multiplexed output. When in lock detect mode, LD does ANDing function on the active PLLs. The RF fractional
test mode is only intended for factory testing.
Lock Detect Output Truth Table
LD [3:0]
0
0
0
0
0
0
1
1
1
1
LD Pin Function
Output Format
Open Drain
Open Drain
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Analog
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
Digital Lock Detect
Analog Lock Detect
Rx R Counter
Rx N Counter
Tx R Counter
Tx N Counter
RF R Counter
RF N Counter
RF Fastlock Timeout Counter
RF Fractional Test Mode
Lock Detect Digital Filter
The Lock Detect Digital Filter compares the difference between the phase of the inputs of the phase detector to a RC generated
delay of approximately 15 ns. To enter the locked state (Lock Det = HIGH) the phase error must be less than the 15 ns RC delay
for five consecutive reference cycles. Once in lock (Lock Det = HIGH), the RC delay is changed to approximately 30 ns. To exit
the locked state (Lock Det = LOW), the phase error must become greater than the 30 ns RC delay. When the PLL is in the pow-
erdown mode, Lock Det is forced HIGH. A flow chart of the digital filter is shown below.
L
www.national.com
12
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