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參數(shù)資料
| 型號： | LM79CCVFX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP44 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 23/31頁 |
| 文件大?。?/td> | 469K |
| 代理商： | LM79CCVFX |
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Block Diagram
Pin Description
Pin
Name(s)
Pin
Number
of Pins
Type
Description
IORD
1
Digital Input
An active low standard ISA bus I/O Read Control.
IOWR
2
1
Digital Input
An active low standard ISA bus I/O Write Control.
SYSCLK
3
1
Digital Input
The reference clock for the ISA bus. Typically ranges from 4.167 MHz to
8.33 MHz. The minimum clock frequency this input can handle is 1 Hz.
D7–D0
4–11
8
Digital I/O
Bi-directional ISA bus Data lines. D0 corresponds to the low order bit,
with D7 the high order bit.
V
CC (+5V)
12
1
POWER
+5V V
CC power. Bypass with the parallel combination of 10 F
(electolytic or tantalum) and 0.1 F (ceramic) bypass capacitors.
GNDD
13
1
GROUND
Internally connected to all digital circuitry.
SMI__IN
14
1
Digital Input
Chainable SMI (System Management Interrupt) Input. This is an active
low input that propagates the SMI signal to the SMI output of the LM79
via SMI Mask Register Bit 6 and SMI enable Bit 1 of the Configuration
Register.
Chassis
Intrusion
15
1
Digital I/O
An active high input from an external circuit which latches a Chassis
Intrusion event. This line can go high without any clamping action
regardless of the powered state of the LM79. The LM79 provides an
internal open drain on this line, controlled by Bit 7 of NMI Mask Register
2, to provide a minimum 20 ms reset of this line.
DS100036-3
LM79
www.national.com
3
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