參數(shù)資料
型號： LM79CCVFX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP44
封裝： 10 X 10 MM, PLASTIC, QFP-44
文件頁數(shù)： 20/31頁
文件大?。?/td> 469K
代理商： LM79CCVFX
Functional Description (Continued)
13.7 SMI Mask Register 2 — Address 44h
Power on default <7:0> = 00h
Bit
Name
Read/
Write
Description
0
IN4
Read/Write
A one disables the corresponding interrupt status bit for SMI interrupt.
1
-IN5
Read/Write
A one disables the corresponding interrupt status bit for SMI interrupt.
2
-IN6
Read/Write
A one disables the corresponding interrupt status bit for SMI interrupt.
3
FAN3
Read/Write
A one disables the corresponding interrupt status bit for SMI interrupt.
4
Chassis Intrusion
Read/Write
A one disables the corresponding interrupt status bit for SMI interrupt.
5
FIFO Overflow
Read/Write
A one disables the corresponding interrupt status bit for SMI interrupt.
6
SMI__IN
Read/Write
A one disables the corresponding interrupt status bit for SMI interrupt.
7
RESET Enable
Read/Write
<7> = 1 in SM Mask Register 2 enables the RESET in the Configuration Register.
13.8 NMI Mask Register 1 — Address 45h
Power on default <7:0> = 00h
Bit
Name
Read/
Write
Description
0
IN0
Read/Write
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
1
IN1
Read/Write
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
2
IN2
Read/Write
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
3
IN3
Read/Write
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
4
Temperature
Read/Write
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
5
BTI
Read/Write
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
6
FAN1
Read/Write
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
7
FAN2
Read/Write
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
13.9 NMI Mask Register 2 — Address 46h
Power on <7:0> = 01000000 binary
Bit
Name
Read/
Write
Description
0
IN4
Read/Write
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
1
-IN5
Read/Write
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
2
-IN6
Read/Write
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
3
FAN3
Read/Write
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
4
Chassis Intrusion
Read/Write
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
5
FIFO Overflow
Read/Write
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
6
SMI__IN
Read/Write
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
Note: The Power on default is 1 for this bit.
7
Chassis Clear
Read/Write
A one outputs a minimum 20 ms active low pulse on the Chassis Intrusion pin. The
register bit self clears after the pulse has been output.
LM79
www.national.com
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