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參數(shù)資料
| 型號： | LM4560VJD |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Advanced PCI Audio Accelerator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 9/54頁 |
| 文件大小： | 380K |
| 代理商： | LM4560VJD |
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3.0 Register Description
(Continued)
When StatusRDY is not active, the chip will retry DMA status
reads if it is not the current active bus master. Whenever chip
retry the DMA status read from other bus master, it will also
generate a bus request for the DMA status read. When the
DMA status read cycle generated by chip is terminated nor-
mally, the chip will write the status data by asserting the Sta-
tusWR signal.
If chip retries a DMA status read from other bus master 3
times without getting the bus ownership or proper data, it will
set the status error bit high which will terminate the pending
DMA status read request internally and ignore the all DMA
status read cycle by the other bus master.
When audio engine receives the StatusWR signal, it will as-
sert the StatusRDY signal and allow the chip to decode I/O
read port 8 normally. The audio engine will de-assert the Sta-
tusRDY after each DMA status read.
Note:
All I/O decoding is 16 bits, write snooping happens only once even with
multiple write retry cycles. Write snooping means chip will decode the
cycle to the audio engine without generating the DEVSEL signal or
TRDY on the PCI bus.
Power Management Configuration (PM_CFG) 46h
Bit 0 (DCC_EN) Dynamic Clock Control Enable
0: Disable
1: Enable. CLKRUN scheme will be enabled.
Bit 1 (DC_PM_EN_) Digital Controller Power Management
Enable
0: Enable When enabled, Audio_clk can be shut off or turn
on according to PM_ST.
1: Disable
Bit 2 (DC_RST) Digital Controller Software Reset
0: normal
1: Reset Digital Controller
Bit 3 (AC_PM_EN_) Analog CODEC Power Management
Enable
0: Enable
If enabled, AC97 bit clock can be shut off according to
PM_ST
1 Disable
Bit 4 (WAKE_EN1) Primary CODEC Wake-up Enable
Read/Write. Powered with Vaux. Cleared when H/W reset or
S/W reset.
0: disable
1: enable
When CODEC_PD = 1, BCLK keeps low, a rising edge of
ACDI1 will set WAVE_EV to high
Bit 5 (WAKE_EN2) Secondary CODEC Wake-up Enable
Read/Write. Powered with Vaux. Cleared when H/W reset or
S/W reset.
0: disable
1: enable
When CODEC_PD = 1, BCLK keeps low, a rising edge of
ACDI2 will set WAVE_EV to high
Bit 6 (ID_WR_EN) Chip IDs write enable
0: Vendor ID, Device ID, Subsystem vendor ID & Subsystem
ID are read only
1: Vendor ID, Device ID, Subsystem vendor ID & Subsystem
ID are writeable.
Bit 7 (TIMER_PME_EN) Inactivity Timer assert PME enable
0: Disable
1: Enable
If enabled, when the Inactivity Timer is expired, PME will be
asserted.
Inactivity Timer Expiration Control 47h
bit 0–7 Inactivity timer expiration base (in seconds)
Each time when audio engine enters into D2 state, the Inac-
tivity timer will load the base count from this register and start
counting at 1s clock rate. When the MSB of the counter goes
from high to low timer has expired. When not in the D2 state,
the timer is reset.
3.1.1.12 INT Acknowledge Snoop Register:
PCI Configuration
Address:
48h–4Bh
Default:
00000000h
Description:
Read/Write
Bit 0 (INTA_SNOOP_ENA) Interrupt Acknowledge Snooping
Enable bit.
0: Disable
1: Enable
Bit 15–7 (INT_VEC) Interrupt Vector to be matched.
All other bits are reserved.
3.1.1.13 Power Management Capability Register (PMC):
PCI Configuration
Address:
DCh–DFh
Default:
66010001h
Description:
Read Only
Bit 7–0 (PM_Cap_ID) Power management capability identi-
fier, read only as 01h.
Bit 15–8 (PM_Next_Ptr) Next data structure item list pointer
in the PCI header, read only as 00h
Bit 31–16 (PM_CAP) Power management capability regis-
ter, read only as E611h.
Bit 31–27 (PME_Support) PME supported PM_ST, read only
as 01100b, indicates that PME can be asserted in D2, D3
hot.
Bit 26 (D2_Support) Read only as 1, indicates D2 supported.
Bit 25 (D1_Support) Read only as 1, indicates D1 supported.
Bit 24–22 Reserved. Read only as 000b.
Bit 21 (DSI) Device Specific Initialization. Read only as 0.
Bit 20 (Vaux) Auxiliary Power Source. Read only as 0.
Bit 19 (PME_clk) PME clock. Read only as 0, indicates that
no PCI clock is required to generate PME.
Bit 18–16 (Version) Read only as 001b, indicates PPMI v1.0
compliance.
3.1.1.14 Power management control/status register
(PMCSR) & PMCSR_BSE & Data:
PCI Configuration
Address:
E0h–E3h
Default:
00000000h
Description:
Read/Write
Bit 31–24 (Data) Read only as 00h.
Bit 23–16 (PMCSR_BSE) Read only as 00h.
Bit 15–0 (PMCSR) Power Management Control/Status Reg-
ister
Bit 15 (PME_Status) Read/Write-Clear.
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