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1.0 Pin Description
(Continued)
1.2 PIN DESCRIPTION
Symbol
V
DD
Pin(s)
20, 39,
52, 53,
69, 83,
100
11, 30,
48, 60,
75, 90
Type
IN
Description
3.3V Power Supply
V
SS
IN
Ground
PCI BUS INTERFACE SIGNALS (51)
AD[31:0]
92–99,
3–10,
21–28,
31–38
C/BE[3:0]
1, 12,
19, 29
I/O
PCI Address/Data Bus.
A time-multiplexed
address data bus.
I/O
PCI Command/Byte
Enable.
Defines the type
of AD bus transaction
type.
Cycle Frame.
A PCI
transaction begins and
ends with the FRAME
signal.
Initiator Ready.
An active
low indicates the cycle
initiator is ready to send
or receive data.
Target Ready.
An active
low indicates that the
target is read to complete
the current transaction.
Device Select.
An active
low indicates the target
has decoded its address.
STOP.
An active low
indicates the target wants
the initiator to stop data
during the current data
phase.
Parity.
Generates an
even parity for the
AD[31.0].
Reset.
A low active signal
which resets the PCI
device.
Interrupt.
An active low
signals in interrupt to the
CPU.
Clock.
The clock that
drives the PCI timing.
Grant.
An active low
signals the master has
access to the PCI bus.
Request.
An active low
indicates the master
wants access to the PCI
bus.
FRAME
13
I/O
IRDY
14
I/O
TRDY
15
I/O
DEVSEL
16
I/O
STOP
17
I/O
PAR
18
I/O
RST
86
IN
INT
84
OUT
PCICLK
87
IN
GNT
88
IN
REQ
89
OUT
Symbol
PCI BUS INTERFACE SIGNALS (51)
CLKRUN
85
Pin(s)
Type
Description
I/O
Clock Run.
An active low
signal used for power
management on
motherboards only. It is
not assigned a pin on the
PCI connector.
Power Management
Event.
An active low
signal used for power
management for add in
cards or motherboards. It
is assigned a pin on the
PCI connector.
Terminal Count.
This
input is asserted by the
DMA controller to indicate
the end of a DMA
transfer. The signal is
only effective during a
DMA access cycle.
Initialization Device
Select.
An active high
allows reads to the PCI
devices configuration
registers.
PME
91
OUT
TC
78
IN
IDSEL
2
IN
MPU-401 INTERFACE SIGNALS (2)
MIDIOUT
50
OUT
MIDI Data Out.
Sends
midi data to the midi
connector.
MIDI Data In.
Receives
midi data from an
optocoupler.
MIDIIN
49
IN
AC97 CODEC INTERFACE SIGNALS (6)
ACRST
57
OUT
AC97 Master Reset.
An
active low which resets
the internal circuitry of
AC97 codecs.
AC97 Bit Clock.
A
12.288 MHz clock from
the codec. This is used to
synchronize the data
streams to and from the
codecs.
AC97 Sync.
Used to start
the data frame used to
format the serial data to
and from the codecs.
Primary CODEC Serial
Data Input.
This receives
serial data in from the
primary codec.
Secondary CODEC
Serial Data Input.
This
receives serial data in
from the secondary
codec.
ACCLK
55
IN
ACSYNC
56
I/O
ACDI1
58
IN
ACDI2
59
IN
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