參數(shù)資料
型號： LM4560VJD
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 消費家電
英文描述： Advanced PCI Audio Accelerator
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： PLASTIC, TQFP-100
文件頁數(shù)： 15/54頁
文件大?。?/td> 380K
代理商： LM4560VJD
3.0 Register Description
(Continued)
Bit7..0
X
Legacy FmMusic Bank 0 Register
Index
Read
Bit 7
1
FmMusic Timer Interrupt Flag (Equal
to Bit 6 + Bit 5)
FmMusic Timer 1 Overflowed Flag
FmMusic Timer2 Overflowed Flag
Reserved
Bit 6
Bit 5
Bit 4..0
1
1
0
Relative Internal Function Register File
In order to emulate the legacy FmMusic(YMF262 or OPL3)
function, a 512 bytes register file (RAM) must be imple-
mented. By legacy access method, this register file has two
banks and the bank index is specified by SBR0 and SBR2
respectively. This register file is byte-wide format, read/write
RAM which has no high speed operation requirement.
Relative Internal Functional Register Extracted From
Legacy FmMusic Bank 0 Register File
FmMusic-TIMER1
Bank Index:
02h
Size:
8 bits
Type:
Read/Write
Default:
00h
Bit 7..0
If enabled, Timer1 counter will increase every 1024AC97 bit-
clock (12.288 MHz). When overflow occurs, this value is re-
loaded into the counter.
FmMusic-TIMER2
Bank Index:
03h
Size:
8 bits
Type:
Read/Write
Default:
00h
X
Timer1 Preset Value
Bit 7..0
If enabled, Timer2 counter will increase every 4096AC97 bit-
clock (12.288 MHz). When overflow occurs, this value is re-
loaded into the counter.
FmMusic-Timer-CONTROL
Bank Index:
04h
Size:
8 bits
Type:
Read/Write
Default:
00h
X
Timer2 Preset Value
Bit 7
1
Reset Bit 7–5 of Legacy FmMusic
Status Register
Reset Timer1 Overflow Flag
Reset Timer2 Overflow Flag
Reserved
Enable Timer 2
Enable Timer 1
Bit 6
Bit 5
Bit 4–2
Bit 1
Bit 0
Bit 7–5 must be self-cleared to 0 after it is written as 1.
When bit 1 or 0 is set from 0 to 1, the corresponding timer
counter will load its preset value and start counting. When
these bits are zero, the respective timer counter will stop
counting. If bit 1 is set 1, bit 7 and 5 of FmMusic Status reg-
1
1
0
1
1
ister will be set 1 when timer2 is overflowed. If bit 0 is set 1,
bit 7 and 6 of FmMusic Status register will be set 1 when
timer1 is overflowed.
3.4.2.2 SBR1 (Legacy FmMusic Bank 0 Register Data
Port)
Address:
AudioBase + 11h or SBBase + 1h or SBBase +
09h or ADLIBBase + 1h or AudioBase + 13h or
SBBase + 3h or ADLIBBase + 3h
Size:
8 bits
Type:
Read/Write
Default:
XXh
Bit 7..0
X
Legacy FmMusic Bank 0 Register
(indexed by SBR0) Data
When writing to this register, if SBR0 is B0h–B8h and bit 5 of
the content (indexed by SBR0) is changed from 0 to 1 or vice
versa, or SBR0 is BDh and any one of bit 4–0 of the content
(indexed by SBR0) is changed from 0 to 1 or vice versa, an
OPL3 Bank0 Key On/Off Dirty Flag will be set in the Audio
Status Registers ASR0 and AOPLSR0.
3.4.2.3 SBR2 (Legacy FmMusic Bank 1 Register Index)
Address:
AudioBase + 12h || SBBase + 2h || ADLIBBase +
2h
Size:
8 bits
Type:
Read/Write
Default:
00h
Bit 7..0
X
Legacy FmMusic Bank 1 Register
Index
3.4.2.4 SBR3 (Legacy FmMusic Bank 1 Register Data
Port)
Address:
AudioBase + 11h or SBBase + 1h or ADLIBBase
+ 1h or AudioBase + 13h or SBBase + 3h or
ADLIBBase + 3h
Size:
8 bits
Type:
Read/Write
Default:
XXh
Bit 7..0
X
Legacy FmMusic Bank 1 Register
(indexed by SBR2) Data
When write to this register, if SBR2 is B0h–B8h and bit 5 of
the content (indexed by SBR2) is changed from 0 to 1 or vice
versa, an OPL3 Bank1 Key On/Off Dirty Flag will be set in
Audio Status Registers ASR0 and AOPLSR0.
3.4.2.5 SBR4 (Legacy Sound Blaster Mixer Register
Index)
Address:
AudioBase + 14h or SBBase + 4h
Size:
8 bits
Type:
Read/Write
Default:
00h
Bit 7..0
X
Legacy SB16 / SBPRO Mixer
Register Index
3.4.2.6 SBR5 (Legacy Sound Blaster Mixer Register
Data Port)
Address:
AudioBase + 15h or SBBase + 5h
Size:
8 bits
Type:
Read/Write
Default:
XXh
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