參數(shù)資料
型號(hào)： LM4560VJD
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 消費(fèi)家電
英文描述： Advanced PCI Audio Accelerator
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： PLASTIC, TQFP-100
文件頁數(shù)： 2/54頁
文件大?。?/td> 380K
代理商： LM4560VJD
Features
(Continued)
n
DirectX timer for video/audio synchronization
n
Forward pin-compatible with future PCI audio
accelerators
n
100-pin TQFP package
n
3.3V operation
Software Support
n
Complete DirectX driver suite (DirectSound3D,
DirectSound, DirectMusic, and DirectInput) for Windows
95 and Windows 98/NT 5.0
n
Configuration installation, and diagnostics under real
mode DOS, WindowsWindows 95, and Windows 98
DOS box
n
Windows 3.1, 95, NT4.0, Windows 98/NT5.0
configuration, installation, and mixer program
n
1, 2, 4, or 8 Mbytes General MIDI (GM)/General Sound
(GS) compliant sample Library
Block Diagram
Table of Contents
1.0 Pin Description
1.1 Package Diagram
1.2 Pin Description
2.0 Functional Decription
2.1 Device Overview
3.0 Register Description
3.1 PCI Configuration Register Map
3.1.1 PCI Configuration Register Description
3.1.1.1 Device ID & Vendor ID
3.1.1.2 Status & Command
3.1.1.3 Class Code & Revision ID
3.1.1.5 Audio IO Base Register
3.1.1.6 Audio MEM Base Register
3.1.1.7 Subsystem ID & Subsystem vendor ID
3.1.1.8 PCIPM Capability List Pointer Register
3.1.1.9 Max_Lat, Min_Gnt, Interrupt Pin & Interrupt Line
3.1.1.10 DDMA Slave Configuration Register
3.1.1.11 Legacy audio/power management configuration
3.1.1.13 Power management capability register (PMC)
3.1.1.14
Power
management
(PMCSR) & PMCSR_BSE & Data
3.2 Audio Processor Register Map
3.3 Audio Processor Register Access Mode
control/status
register
3.3.1 I/O Access Mode
3.3.2 Memory Access Mode
3.4 Audio Processor Register Description
3.4.1 DMA Registers
3.4.1.1 DMAR0 (Legacy DMA Playback Buffer Base Regis-
ter Port1)
3.4.2 Legacy Sound Blaster/Adlib Registers
3.4.3 Legacy MPU-401 Registers
3.4.4 Legacy Gameport Register
3.4.5 Serial Interface Control Register
3.4.6 Misc and Status Register
3.4.7 OPL3 Channel Status Register
3.4.8 S/PDIF & GPIO Registers
3.4.9 Wave Engine Registers
3.4.9.31 F4h_A (EBUF1) ( Bank A Only)
4.0 Functional Description
4.1 Wave Engine
4.1.1 Scheduler
4.1.2 Address Engine
4.1.3 Envelope Engine
4.1.4 Interpolation & Volume Adjustment
4.1.5 Digital Mixer
4.1.6 LFO
4.1.7 Recording
DS100910-1
www.national.com
2
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