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參數(shù)資料
| 型號(hào)： | LM4560VJD |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Advanced PCI Audio Accelerator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 23/54頁 |
| 文件大?。?/td> | 380K |
| 代理商： | LM4560VJD |
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3.0 Register Description
(Continued)
This bit will be set from ‘0’ to ‘1’ only when a ‘1’ is written to
the corresponding bit in register START_A.
Writing to this I/O port means issuing a start command to ad-
dress engine and envelope engine in expected channel.
0: Ignore.
A ‘0’ written to bit n will not change the status of channel n.
1: Start.
A ‘1’ written to bit n will start channel n’s address engine and
envelope engine and also set the status bit n to ‘1’.
3.4.9.2 STOP_A (Channel STOP Command and Status
Register for Bank A)
Address:
AudioBase + 84h
Size:
32 bits
Type:
Read/Write
Default:
00000000h
Reading from this I/O port will return the same value as from
the last register START_A.
Writing to this I/O port means issuing a stop command to ad-
dress engine and envelope engine in expected channel.
0: Ignore.
A ‘0’ written to bit n will not change the status of channel n.
1: Stop.
A ’1’ written to bit n will stop channel n’s address engine and
envelope engine, and also reset the corresponding status bit
to ‘0’.
3.4.9.3 DLY (Delay Flag of Bank A)
Address:
AudioBase + 88h
Size:
32 bits
Type:
Read/Write
Default:
00000000h
When read, this register will show the delay status of each
channel of Bank A. Bit n is for channel n.
0: normal
This bit will toggle from ‘1’ to ‘0’ when envelope engine
change from a delay mode buffer to a non-delay mode
buffer. When channel n is stopped, bit n will be reset to ‘0’.
1: channel is currently in delay mode (address engine kept
stopped but envelope engine is running).
This bit will toggle from ‘0’ to ‘1’ only when envelope engine
begin to deal with a delay mode buffer.
When write,
0: ignore (don’t change)
1: set to ‘1’
3.4.9.4 SIGN_CSO (Sign bit of CSO) (for Bank A only)
Address:
AudioBase + 8Ch
Size:
32 bits
Type:
Read/Write
Default:
00000000h
This register is used to store the sign bits of 32 channel’s
CSO of Bank A, with ‘0’ means current sample address is
greater than or equal to LBA(Loop Begin Address), while ‘1’
means current sample address is less than or equal to LBA.
This register can be programmed with an initial status and
will be updated by address engine.
Write ‘0’: ignore (don’t change)
Write ‘1’: set to ‘1’
When channel n is stopped, bit n will be reset to ‘0’.
3.4.9.5 CSPF_A (Bank A Current Sample Position Flag)
Address:
AudioBase + 90h
Size:
32 bits
Type:
Read/Write
Default:
00000000h
This register will show a flag which indicates the Bank A’s
current sample is in a range between ESO/2 to ESO or in a
range before ESO/2 (ESO is offset from loop begin to loop
end). And this flag will be used for sample data double buff-
ering control. Bit n is for channel n.
0: Before ESO/2
1: From ESO/2 to ESO
When channel n is stopped, bit n will be reset to ‘0’.
3.4.9.6 CEBC (Current Envelope Buffer Control) (for
Bank A only)
Address:
AudioBase + 94h
Size:
32 bits
Type:
Read/Write
Default:
00000000h
Reading from this register will return current envelope buffer
flags of 32 channels of Bank A, which indicate currently en-
velope engine is using parameters from EBUF1 or EBUF2.
Bit n is for channel n.
0: Buffer 1
1: Buffer 2
Writing ‘1’ to bit n of this register will toggle the flag in chan-
nel n and force envelope engine to change buffer. Writing ’0’
to bit n won’t change anything in channel.
0: Ignore
1: Toggle
When channel n is stopped, bit n will be reset to ‘0’.
3.4.9.7 AINT_A (Bank A Address Engine Interrupt)
Address:
AudioBase + 98h
Size:
32 bits
Type:
Read/Write
Default:
00000000h
Any bits toggled from ‘0’ to ‘1’ will result in a IRQ.
Reading from this I/O port will return the address INT status
of Bank A’s 32 channels. Bit n is for channel n.
0: No INT
1: INT
This bit will be set in 2 cases:
When CSO (current sample offset)
≥
ESO (end sample off-
set), and ENDLP_IE (end of loop INT enable bit in Global
Control register) =1 and AINTEN_A bit n is set 1 for channel
n.
When CSO (current sample offset)
≥
ESO/2 (middle of
ESO), and MIDLP_IE (middle of loop INT enable bit in Glo-
bal Control register) =1 andAINTEN_Abit n is set 1 for chan-
nel n.
Writing ‘1’ to bit n of this register will reset this bit.
0: Ignore.
A ‘0’ written to bit n will not change the status of this bit.
1: reset
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