參數(shù)資料
型號: LH7A404N0F000B3
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學處理器
英文描述: 32-Bit System-on-Chip
封裝: LH7A404N0F000B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT1021-1.html<1<Always Pb-free,;LH7A404N0F092B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT
文件頁數(shù): 63/75頁
文件大?。?/td> 1109K
代理商: LH7A404N0F000B3
32-Bit System-on-Chip
LH7A404
Preliminary data sheet
63
NXP Semiconductors
Clock and State Controller
(CSC) Waveforms
Figure 48 shows the behavior of the LH7A404 when
coming out of Reset or Power-On. Table 13 gives the
timing parameters.
At Power-On, nPOR must be held LOW until the
32.768 kHz oscillator is stable, and must be deasserted
at least two 1 Hz clock periods before the WAKEUP
signal is asserted. Once the 14.7456 MHz oscillator is
stable, the PLLs require 250 μs to lock.
On transition from Standby to Run (including a Cold
Boot), the Wakeup pin must not be asserted for two 1
Hz clock periods after assertion of nPOR to allow time
for sampling BATOK and nEXTPWR. The delay
prevents a false ‘battery good’ indication caused by
alkaline battery recovery that can immediately follow a
battery-low switch off.
nRESETOUT Timing Sequence
Timing for the nRESETOUT sequence is shown for
each of the three reset triggers (nPOR, nURESET, and
nPWRFL) in Figure 49 through Figure 51, and timing
values are presented in Table 14 through Table 16.
NOTE:
*VDDC = VDDCmin
NOTE: *
The timing relationship is specified as a cycle-based timing. Due to variations in crystal input clock jitter,
power rail noise and I/O conditioning these timings will vary marginally. It is recommended that designers
Table 13. Reset AC Timing
PARAMETER
DESCRIPTION
MIN.
MAX.
UNIT
tOSC32 (32 kHz)
32.768 kHz Oscillator Stabilization Time after Power On*
550
ms
tOSC14 (14 MHz)
14.7456 MHz Oscillator Stabilization Time after WAKEUP
2.5
ms
Figure 48. PLL Start-up
LH7A404-22
tOSC32
VDDC
VDDCmin
XTAL32
nPOR
tOSC14
XTAL14
WAKEUP
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