參數(shù)資料
型號: LH7A404N0F000B3
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: 32-Bit System-on-Chip
封裝: LH7A404N0F000B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT1021-1.html<1<Always Pb-free,;LH7A404N0F092B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT
文件頁數(shù): 12/75頁
文件大?。?/td> 1109K
代理商: LH7A404N0F000B3
LH7A404
32-Bit System-on-Chip
12
Preliminary data sheet
NXP Semiconductors
NOTES:
1. Signals beginning with ‘n’ are Active LOW.
2. The SCLK pin can source up to 12 mA and sink up to 20 mA.
See ‘DC Characteristics’.
3. Schmitt trigger input; see ’DC Specifications’, page 31 for triggers
points and hysteresis.
4. These pins have alternate NAND Flash functions during boot-up
when using the internal Boot ROM. Consult the Boot ROM
Chapter of the User’s Guide for more information.
5. The nWAIT pin must be pulled HIGH with a 33 k
resistor to avoid
the possibility of the SMC inadvertently going into WAIT.
6. The internal pullup and pulldown resistance on all digital I/O pins
is 50K
.
U13
AN3/LR/Y-
ADC channel 3
Touch Screen Controller Lower Right
Touch Screen Controller Y-minus
Input
Input
I
V14
AN4/WIPER
ADC channel 4
Wiper input from 5-wire Touch Screen
Input
Input
I
U14
VSS or VSSA
Connect pin to either VSS or VSSA
Input
Input
I
V15
AN6
ADC channel 6
Input
Input
I
W15
AN7
ADC channel 7
Input
Input
I
T13
AN8
ADC channel 8
Input
Input
I
Y14
AN9
ADC channel 9
Input
Input
I
E12
SCIO
Smart Card Interface I/O
LOW
LOW
12 mA
I/O
A11
SCCLK
Smart Card Interface Clock
LOW
LOW
12 mA
I/O
B11
nSCRESET
Smart Card Interface Reset
LOW
LOW
12 mA
O
B10
SCVCCEN
Smart Card Interface VCC Enable
LOW
No Change
12 mA
O
D6
CTCLKIN
Counter Timer Clock Input
Input
No Change
I
A3
DREQ0
DMA Request 0
Input
No Change
I
D5
DACK0
DMA Acknowledge 0
Input
No Change
12 mA
I/O
C4
DEOT0
DMA End of Transfer 0
Input
No Change
12 mA
I/O
B3
DREQ1
DMA Request 1
Input
No Change
I
A2
DACK1
DMA Acknowledge 1
Input
No Change
12 mA
I/O
E5
DEOT1
DMA End of Transfer 1
Input
No Change
12 mA
I/O
U16
nTEST0
Test Pin 0. Internal weak pull up to VDD. Status
latched at nPOR going HIGH. Pull LOW for JTAG
mode. Pull HIGH (or leave open) for Normal mode.
See Table 3.
Input with
pull-up
Input with
pull-up
I
W18
nTEST1
Test Pin 1. Internal weak pull up to VDD. Status
latched at nPOR going HIGH. Pull HIGH (or leave
open) for both JTAG and Normal mode. See Table 3.
Input with
pull-up
Input with
pull-up
I
D3
TDI
JTAG Data In. Internal weak pull up to VDD.
Input
No Change
I
C2
TCK
JTAG Clock. Internal weak pull up to VDD.
Input
No Change
I
3
B1
TDO
JTAG Data Out
High Z
No Change
4 mA
O
E3
TMS
JTAG Test Mode Select. Internal weak pull up to
VDD.
Input
No Change
I
Table 2. LH7A404 Functional Pin List (Cont’d)
LFBGA
SIGNAL
DESCRIPTION
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE
I/O NOTES
Table 3. nTEST Pin Function
MODE
nTEST0
nTEST1
nURESET
JTAG
0
1
1
Normal
1
1
x
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