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參數(shù)資料
| 型號： | LH7A404N0F000B3 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)學處理器 |
| 英文描述： | 32-Bit System-on-Chip |
| 封裝： | LH7A404N0F000B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT1021-1.html<1<Always Pb-free,;LH7A404N0F092B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT |
| 文件頁數(shù)： | 27/75頁 |
| 文件大小： | 1109K |
| 代理商： | LH7A404N0F000B3 |
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32-Bit System-on-Chip
LH7A404
Preliminary data sheet
27
NXP Semiconductors
UART/IrDA
The LH7A404 contains three UARTs; UART1,
UART2, and UART3.
The UART performs:
Serial-to-Parallel conversion on data received from
the peripheral device
Parallel-to-Serial conversion on data transmitted to
the peripheral device.
The transmit and receive paths can both be routed
through the DMA separately or simultaneously, and are
buffered with internal FIFO memories. This allows up to
16 bytes to be stored independently in both transmit and
receive modes. The UART can generate:
Four individually maskable interrupts from the
receive, transmit, and modem status logic blocks
A single combined interrupt so that the output is
asserted if any of the individual interrupts are
asserted and unmasked.
If a framing, parity or break error occurs during
reception, the appropriate error bit is set and stored in
the FIFO. If an overrun condition occurs, the overrun
register bit is set immediately and the FIFO data is pre-
vented from being overwritten. UART1 also supports
IrDA 1.0 (15.2 kbit/s).
The modem status input signals Clear to Send
(CTS), Data Carrier Detect (DCD) and Data Set Ready
(DSR) are supported on UART2 and UART3.
Timers
The LH7A404 includes three programmable timers.
Each of the timers can operate in two modes: free run-
ning and pre-scale. The timers are programmed using
four registers; Load, Value, Control, and Clear.
Two identical timers, Timer 1 (TC1) and Timer 2
(TC2), use clock sources of either 508 kHz or 2 kHz. The
clock source and mode are selectable by writing to the
appropriate bits in the system control register. Each
timer has a 16-bit read/write data register and a control
register. The timer is immediately loaded with the value
written to the data register. This value is then decre-
mented on the next active clock edge to arrive after the
write. When the timer underflows, it immediately asserts
its appropriate interrupt.
Timer 3 (TC3) has the same basic operation, but is
clocked from a single 7.3728 MHz source. Once the
timer has been enabled and written to, it decrements
on the next rising edge of the 7.3728 MHz clock after
the data register has been updated.
FREE-RUNNING MODE
In free-running mode, the timer wraps around to
0xFFFF when it underflows and continues counting down.
PRE-SCALE MODE
In pre-scale (periodic) mode, the value written to
each timer is automatically re-loaded when the timer
underflows. This mode can be used to produce a pro-
grammable frequency to drive the buzzer or generate a
periodic interrupt.
Real Time Clock (RTC)
The RTC provides a basic alarm function or long
time-base counter. This is achieved by generating an
interrupt signal after counting for a programmed num-
ber of cycles of a real-time clock input. Counting in one-
second intervals is achieved by use of a 1 Hz clock
input to the RTC.
Keyboard and Mouse Interface (KMI)
The Keyboard and Mouse Interface has the
following features:
IBM PS/2 or AT-compatible keyboard or mouse
interface
Half-duplex, bidirectional synchronous serial inter-
face using open-drain outputs for clock and data.
Programmable 4-bit reference clock divider
Polled or interrupt-driven mode
Separately maskable transmit and receive interrupts
Single combined interrupt output
Odd parity generation and checking
Register bits for override of keyboard clock and
data lines.
Additional test registers and modes are implemented
for functional verification and manufacturing test.
A/D Converter with Brownout Detector and
Touch Screen Controller
The LH7A404 includes an A/D Converter (ADC) with
integrated Touch Screen Controller (TSC) and brown-
out detector. The TSC is a complete interface to a
Touch Screen for portable personal devices. It com-
bines the front-end biasing and control circuitry with
A/D conversion, reference generation, and digital inter-
face functions to completely replace external ICs used
to implement this interface. The ADC features:
A 10-bit A/D converter with integrated sample-and-
hold, fully differential, high impedance signal and ref-
erence inputs
Active matrix for bias and control circuits necessary
for connection to external 4-, 5-, 7-, and 8-wire touch
panels, including pen pressure implementation
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LH7A404N0F000B3,55 | 功能描述:ARM微控制器 - MCU LCD,USB FS/HOST,MMU,ADC,BGA324 RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LH7A404N0F000B3,551 | 制造商:NXP Semiconductors 功能描述: |
| LH7A404N0F000B3;55 | 功能描述:ARM微控制器 - MCU LCD USB FS/HOST MMU RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LH7A404N0F000B3;55 | 制造商:NXP Semiconductors 功能描述:IC 32BIT MCU 200MHZ LFBGA-324 |
| LH7A404N0F000B3-S | 功能描述:ARM微控制器 - MCU ARM9 LCD USB HOST RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
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