參數(shù)資料
型號: LH7A404N0F000B3
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學處理器
英文描述: 32-Bit System-on-Chip
封裝: LH7A404N0F000B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT1021-1.html<1<Always Pb-free,;LH7A404N0F092B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT
文件頁數(shù): 35/75頁
文件大?。?/td> 1109K
代理商: LH7A404N0F000B3
32-Bit System-on-Chip
LH7A404
Preliminary data sheet
35
NXP Semiconductors
AC Specifications
All signals described in Table 12 relate to transi-
tions following an internal reference clock signal.
The illustration in Figure 7 represents all cases of
these sets of measurement parameters.
The reference clock signals in this design are:
HCLK, internal System Bus clock (‘C’ in timing data)
PCLK, the Peripheral Bus clock
SSPCLK, the Synchronous Serial Port clock
UARTCLK, the UART Interface clock
LCDDCLK, the LCD Data clock from the
LCD Controller
ACBITCLK, the AC97 and ACI clock
SCLK, the Synchronous Memory clock.
All signal transitions are measured from the 50 %
point of the clock to the 50 % point of the signal.
For outputs from the LH7A404, tOVXXX (e.g. tOVA)
represents the amount of time for the output to become
valid from the rising edge of the reference clock signal.
Maximum requirements for tOVXXX are shown in
Table 12.
The signal tOHXXX (e.g. tOHA) represents the
amount of time the output must be held valid after the
rising edge of the reference clock signal. Minimum
requirements for tOHXXX are listed in Table 12.
For inputs, tISXXX (e.g. tISD) represents the
amount of setup time the input signal must be valid after
a valid address bus, or rising edge of the peripheral
clock. Maximum requirements for tISXXX are shown in
Table 12.
The signal tIHXXX (e.g. tIHD) represents the
amount of time the output must be held valid following
the rising edge of the reference clock signal. Minimum
requirements are shown in Table 12.
Figure 7. LH7A404 Signal Timing
REFERENCE
CLOCK
OUTPUT
SIGNAL (O)
INPUT
SIGNAL (I)
tOVXXX
tOHXXX
tISXXX tIHXXX
LH7A404-9
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