參數(shù)資料
型號: LH7A404N0F000B3
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: 32-Bit System-on-Chip
封裝: LH7A404N0F000B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT1021-1.html<1<Always Pb-free,;LH7A404N0F092B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT
文件頁數(shù): 19/75頁
文件大小: 1109K
代理商: LH7A404N0F000B3
32-Bit System-on-Chip
LH7A404
Preliminary data sheet
19
NXP Semiconductors
Power Modes
The LH7A404 has three operational states: Run,
Halt, and Standby. During Run all clocks are hardware
enabled and the processor is clocked. In the Halt mode
the device is functioning, but the processor clock is
halted while it waits for an event such as a key press.
Standby equates to the computer being switched ‘off’,
i.e. no display (LCD disabled) and the main oscillator is
shut down.
Reset Modes
Three external signals can generate resets to the
LH7A404: nPOR (power on reset), nPWRFL (power
failure) and nURESET (user reset). If any of these are
active, a system reset is internally generated. An nPOR
reset performs a full system reset. The nPWRFL and
nURESET resets perform a full system reset except for
the SDRAM refresh control, SDRAM Global Configura-
tion, SDRAM Device Configuration, and the RTC
peripheral registers. The SDRAM controller issues a
self-refresh command to external SDRAM before the
system enters an nPWRFL and nURESET reset. This
allows the system to maintain its Real Time Clock and
SDRAM contents. Upon release of Reset, the chip
enters Standby mode. Once in the Run mode the
PWRSR register can be interrogated to determine the
nature of the reset and the trigger source, after which
software can then take appropriate actions.
Data Paths
The data paths in the LH7A404 are:
The AMBA AHB bus
The AMBA APB bus
The External Bus Interface
The LCD AHB bus
The DMA busses.
AMBA AHB BUS
The Advanced Microprocessor Bus Architecture
AHB (AMBA AHB) is a high speed 32-bit-wide data bus.
The AMBA AHB is for high-performance, high-clock-fre-
quency system modules.
LH7A404 peripherals and memory with high band-
width requirements are connected to the ARM922T
processor and other bus masters using a multi-master
AHB bus. These peripherals include the external mem-
ory interfaces, on-chip SRAM, LCD Controller (bus
master), DMA Controller (bus master), and USB Host
(bus master). Remaining peripherals reside on the
lower bandwidth Advanced Peripheral Bus (APB),
which is accessed from the AHB via the APB Bridge.
The APB Bridge is the only master on the APB, and its
operation is transparent to the user as it converts AHB
accesses into slower APB accesses automatically.
Figure 3. Clock and State Controller Block Diagram
IN
14.7456 MHz
LH7A404-6
500 kHz
MIN.
HCLKDIV
GCLK
MUST BE
BETWEEN
80 and 400 MHz
PCLKDIV
FCLK
HCLK
HCLK_CPU
PCLK
32.768 kHz
RTC OSC
GATE
GATE
DIVIDE BY
PREDIV+2
DIVIDE
BY 2
VCO
PLL1
MAIN DIVIDER 1:
DIVIDE BY MAINDIV1+2
MAIN DIVIDER 2:
DIVIDE BY MAINDIV2+2
32.768 kHz
RTC
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