參數(shù)資料
型號: LH7A404N0F000B3
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: 32-Bit System-on-Chip
封裝: LH7A404N0F000B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT1021-1.html<1<Always Pb-free,;LH7A404N0F092B3<SOT1021-1 (LFBGA324)|<<http://www.nxp.com/packages/SOT
文件頁數(shù): 32/75頁
文件大小: 1109K
代理商: LH7A404N0F000B3
LH7A404
32-Bit System-on-Chip
32
Preliminary data sheet
NXP Semiconductors
Analog-To-Digital Converter
Electrical Characteristics
Table 9 shows the derated specifications for
extended temperature operation. See Figure 6 for the
ADC transfer characteristics.
NOTES:
1. The analog section of the ADC takes 16 × A2DCLK cycles per conversion,
plus 1 × A2DCLK cycles to be made available in the PCLK domain. An additional
3 × PCLK cycles are required before being available on the APB.
2. Data out = 0000000000 when the analog input equals the negative reference.
Data out = 1111111111 when the analog input equals the positive reference.
3. Guaranteed monotonic.
4. INL calculated as deviation from ‘best fit’ line after subtracting offset/gain errors over the center
90 % of full scale output range.
5. DC voltage error for the transition voltage from code 511 (0x1FF) to 512 (0x200)
6. The internal voltage reference is driven to nominal value VREF = 2.0 V. Using the Reference Multiplexer,
alternative low impedance (RS < 500) voltages can be selected as reference voltages.
The range of voltages allowed are specified above.
7. The analog input pins can be driven anywhere between the power supply rails.
If the voltage at the input to the ADC exceeds VREF+ or is below VREF-, the A/D result will saturate appropriately
at positive or negative full scale. Trying to pull the analog input pins above or below the power supply rails will
cause protection diodes to be forward-biased, resulting in large current source/sink and possible damage to the ADC.
8. Bandgap and other low-bandwidth circuitry operating. All other ADC blocks shut down.
Table 9. ADC Electrical Characteristics
PARAMETER
MIN.
TYP.
MAX.
UNITS
NOTES
A/D Resolution
10
10
Bits
Throughput Conversion
17
CLK Cycles
1
Acquisition Time
3
CLK Cycles
Data Format
binary
2
Clk Frequency
500
5,000
ns
Differential Non-Linearity (DNL)
-0.99
+4.5
LSB
3
Integral Non-Linearity (INL)
-4.5
+4.5
LSB
4
Offset Error
+35
+50
mV
5
Gain Error
-4.0
4.0
LSB
Reference Voltage Output
1.85
2.0
2.15
V
VREF-
VSSA
VSSA
(VREF+) -1.0
V
6
VREF+
(VREF-) +1.0
VREF
VDDAD
V
6
Crosstalk between channels
-60
dB
Analog Input Voltage Range
0
VDDAD
V
μ
A
μ
A
7
Analog Input Current
5
Reference Input Current
5
Analog Input capacitance
15
pF
Operating Supply Voltage
3.0
3.6
V
μ
A
μ
A
μ
A
Operating Current, VDDAD
590
1000
Standby Current, VDDAD
180
8
Stop Current, VDDAD
1
Brownout Trip Point (falling point)
2.36
2.63
2.9
V
Brownout Hysteresis
120
mV
Operating Temperature
40
85
°C
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