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參數(shù)資料
| 型號： | L99PM62XP |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 電源管理 |
| 英文描述： | 4-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO36 |
| 封裝： | ROHS COMPLIANT, POWERSSO-36 |
| 文件頁數(shù)： | 19/98頁 |
| 文件大?。?/td> | 1117K |
| 代理商： | L99PM62XP |
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Description
L99PM62XP
Doc ID 16363 Rev 2
system. The forced VBAT standby mode can be terminated by any regular wake-up event.
The root cause of the forced VBAT standby is indicated in the SPI status registers
The forced VBAT standby mode is entered in case of:
●
Multiple watchdog failures: forced sleep WD = 1 (15x watchdog failure)
●
Multiple thermal shutdown 2: forced sleep TSD2/SHTV1 = 1 (7x TSD2)
●
V1 short at turn-on: forced sleep TSD2/SHTV1 = 1 (V1 < V1fail for t > 4 ms)
Figure 16. Example: exit fail safe mode from watchdog failure
2.6
Reset output (NRESET)
If V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output
“NRESET” is pulled up by internal pull up resistor to V1 voltage after a 2 ms reset delay time.
Table 6.
Persisting fail safe conditions and exit modes
Failure source
Failure condition
Diagnosis
Exit from fail-safe mode
C (oscillator)
15 consecutive
watchdog failures
Fail-safe = 1
ForcedSleepWD = 1
Wake-up
TRIG = 1 during LOWi
read & clear SR3
V1
short at turn-on
Fail-safe = 1
ForcedSleepTSD2/SHTV1 = 1
Read&clear SR3 after wake-up
Temperature
7 times TSD2
Fail-safe = 1
TW = 1
TSD1 = 1
TSD2 = 1
ForcedSleepTSD2/SHTV1 = 1
Read&clear SR3 after wake-up
write operation
Ctrl Reg 3 WD Time
[e.g. 50 ms]
Feedback:
FSO = 1
write operation blocked
CSN
write operation
Ctrl Reg 1 Trig = 1
Feedback:
FSO = 1
provide propper trigger
read operation
any valid address
Feedback:
check FSO = 1
quit fail safe mode
long open window
window mode
Fail Safe Mode active
Fail Safe Mode inactive
SPI
Command
SPI
Feedback
Watchdog
Mode
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