參數(shù)資料
型號(hào): L6740LTR
廠商: 意法半導(dǎo)體
英文描述: Hybrid controller (4+1) for AMD SVID and PVID processors
中文描述: 混合控制器(4 1對(duì)AMD SVID和PVID)處理器
文件頁(yè)數(shù): 40/44頁(yè)
文件大?。?/td> 657K
代理商: L6740LTR
LTB technology
L6740L
40/44
Gain Design.
Through the LTBGAIN pin it is possible to modify the slope of the LTB
Ramp in order to modulate the entity of the LTB response once the LT has been
detected. In fact, the response depends on the board design and its parasitics requiring
different actions from the controller.
Leaving the LTBGAIN pin floating, the maximum pulse-width is programmed. The slope
of the LTB ramp will be equal to 1/2 of the OSC ramp slope.
Connecting R
LTBGAIN
to GND, the LTB Ramp slope can be modified as follow:
Where I
LTBGAIN
is the current sunk from LTBGAIN pin and I
OSC
is the OSC current
(20
μ
A plus the current sunk from the OSC pin).
LTB Technology
TM
Design Tips.
Decrease R
LTB
to increase the system sensitivity making the system sensitive to
smaller dV
OUT
.
Increase C
LTB
to increase the system sensitivity making the system sensitive to
higher dV/dt.
Increase R
LTBGAIN
to increase the width of the LTB pulse reducing the system
ring-back.
LTBRamp
Slope
OSC
Slope
1
I
I
OSC
-----------------------
+
=
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