參數(shù)資料
型號(hào): L6740LTR
廠商: 意法半導(dǎo)體
英文描述: Hybrid controller (4+1) for AMD SVID and PVID processors
中文描述: 混合控制器(4 1對(duì)AMD SVID和PVID)處理器
文件頁(yè)數(shù): 33/44頁(yè)
文件大小: 657K
代理商: L6740LTR
L6740L
Output voltage monitoring and protections
33/44
Figure 13.
FB disconnection protection
7.3
PWRGOOD
It is an open-drain signal set free after the soft-start sequence has finished; it is the logic
AND between the internal CORE and NB PGOOD (or just the CORE PGOOD in PVI mode).
It is pulled low when the output voltage of one of the two sections drops 250mV below the
programmed voltage. It is masked during On-The-Fly VID Transitions as well as when the
CORE section is set to OFF (from SVI bus) while the NB Section is still operative.
7.4
Over-current
The Over Current threshold has to be programmed to a safe value, in order to be sure that
each Section doesn't enter OC during normal operation of the device. This value must take
into consideration also the extra current needed during the OTF-VID Transition (I
OTF-VID
)
and the process spread and temperature variations of the sensing elements (DCR and
R
dsON
).
Moreover, since also the internal threshold spreads, the design has to consider the mini-
mum/maximum values of the threshold. Considering the reading method, the two sections
will show different behaviors in OC.
7.4.1
CORE section
L6740L performs two different OC protections for the CORE Section: it monitors both the
average current and the per-phase current and allows to set an OC threshold for both.
OC_PHASE pin allows to define a maximum information current per-phase
(I
INFOx
). A R
OC_TH
resistor connected to SGND allows to define an end-of-scale
current (I
OC_TH
) that is compared with the information current generated for each
phase (I
INFOx
). If the current information for the single phase exceed the
programmed end-of-scale current (i.e. if I
INFOx
> I
OC_TH
), the device will turn-on
the LS mosfet until the threshold is re-crossed (i.e. until I
INFOx
< I
OC_TH
).
OC_AVG pin allows to define a maximum total output current for the system
(I
OC_AVG
). A copy of the DROOP current is sourced from the OC_AVG/LI pin. By
connecting a resistor R
OC_AVG
to SGND, a load indicator with 2.5V (V
OC_AVGTH
)
end-of-scale can be implemented. This means that when the voltage present at
the LI pin crosses V
OC_AVGTH
, the device detects an average OC (OC_AVG) and
immediately latches with all the mosfets of all the sections OFF (HiZ).
CORE_REFERENCE
FB
COMP
VSEN
FBG
R
F
C
F
R
FB
To VDD_CORE
from DAC...
NB_REFERENCE
NB_FB
NB_COMP
NB_VSEN
NB_FBG
R
F_NB
C
F_NB
R
FB_NB
(Remote Sense)
CORE SECTION - VSEN AND FBG DISCONNECTION
NB SECTION - NB_VSEN AND NB_FBR DISCONNECTION
500mV
FBG DISCONNECTED
CS1-
VSEN
DISCONNECTED
3
μ
A
5
μ
A
from DAC...
500mV
FBG DISCONNECTED
600mV
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