參數(shù)資料
型號: L6740LTR
廠商: 意法半導(dǎo)體
英文描述: Hybrid controller (4+1) for AMD SVID and PVID processors
中文描述: 混合控制器(4 1對AMD SVID和PVID)處理器
文件頁數(shù): 27/44頁
文件大?。?/td> 657K
代理商: L6740LTR
L6740L
Output voltage positioning
27/44
6.6
NB section - Load-line and load-indicator (Optional)
This method introduces a dependence of the output voltage on the load current recovering
part of the drop due to the output capacitor ESR in the load transient. Introducing a depen-
dence of the output voltage on the load current, a static error, proportional to the output cur-
rent, causes the output voltage to vary according to the sensed current.
Figure 10
shows the Current Sense Circuit used to implement the Load-Line. The current
flowing across the Low-Side MOSFET is read through R
ISEN
. R
ISEN
programs a transcon-
ductance gain and generates a current I
ISEN
proportional to the current delivered by the NB
Section that is then sourced by the NB_FB pin (I
DROOP_NB
). R
FB_NB
gives the final gain to
program the desired load-line slope (
Figure 9
).
The output characteristic vs. load current is then given by (Offset disabled):
Where R
LL_NB
is the resulting Load-Line resistance implemented by the NB Section.
The whole power supply can be then represented by a “real” voltage generator with an
equivalent output resistance R
LL_NB
and a voltage value of VID.
R
FB_NB
resistor can be then designed according to the R
LL_NB
specifications as follow:
Caution:
Load-Line (DROOP) implementation is optional, in case it is not desired, the resulting cur-
rent information may be employed for other purposes, such as Load Indicator (LI). In this
case, simply connect a resistor R
LI_NB
to SGND: the resulting voltage drop across R
LI_NB
will be proportional to the delivered current according to the following relationship:
R
R
ISEN
Note:
Split between R
FB_COMP_NB
and R
FB_DROOP_NB
(
Figure 9
) is useful in custom designs
where the Droop effect is minimum (i.e. <50mV over 100A) to simplify the compensation
network design.
6.7
NB section - Offset (Optional)
The NB_OS pin allows programming a positive offset (V
OS_NB
) for the NB Section output
voltage by connecting a resistor R
OS_NB
to SGND. The pin is internally fixed at 1.240V so a
current is programmed by connecting the resistor R
OS_NB
between the pin and SGND: this
current is mirrored and then properly sunk from the NB_FB pin as shown in
Figure 9
. Output
voltage is then programmed as follow:
Offset resistor can be designed by considering the following relationship (R
FB_NB
may be
fixed by the Droop effect):
V
OUT_NB
VID
R
FB_NB
I
DROOP_NB
VID
R
FB_NB
R
R
ISEN
----------------
I
OUT
VID
R
LL_NB
I
OUT_NB
=
=
=
R
FB_NB
R
LL_NB
R
R
dsON
-----------------
=
V
NB_DROOP
R
LI_NB
----------------
I
OUT_NB
=
V
NB
VID
R
FB_NB
I
DROOP_NB
I
OS_NB
(
)
=
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