參數(shù)資料
型號(hào): L6740LTR
廠商: 意法半導(dǎo)體
英文描述: Hybrid controller (4+1) for AMD SVID and PVID processors
中文描述: 混合控制器(4 1對(duì)AMD SVID和PVID)處理器
文件頁(yè)數(shù): 25/44頁(yè)
文件大?。?/td> 657K
代理商: L6740LTR
L6740L
Output voltage positioning
25/44
Figure 10.
Current reading - CORE section (left) and NB section (right)
The current read through the CSx+ / CSx- pairs is converted into a current I
INFOx
propor-
tional to the current delivered by each phase and the information about the average current
I
AVG
=
Σ
I
INFOx
/ N is internally built into the device (N is the number of working phases). The
error between the read current I
INFOx
and the reference I
AVG
is then converted into a voltage
that with a proper gain is used to adjust the duty cycle whose dominant value is set by the
voltage error amplifier in order to equalize the current carried by each phase.
6.3
CORE section - Load-line and load-indicator (Optional)
L6740L is able to introduce a dependence of the output voltage on the load current recover-
ing part of the drop due to the output capacitor ESR in the load transient. Introducing a
dependence of the output voltage on the load current, a static error, proportional to the out-
put current, causes the output voltage to vary according to the sensed current.
Figure 10
shows the Current Sense Circuit used to implement the Load-Line. The current
flowing across the inductor(s) is read through the R - C filter across CSx+ and CSx- pins. R
G
programs a transconductance gain and generates a current I
CSx
proportional to the current
of the phase. The sum of the I
CSx
current is then sourced by the FB pin (I
DROOP
). R
FB
gives
the final gain to program the desired load-line slope (
Figure 9
).
Time constant matching between the inductor (L / DCR) and the current reading filter (RC)
is required to implement a real equivalent output impedance of the system so avoiding over
and/or under shoot of the output voltage as a consequence of a load transient. See
Section 6.2
. The output characteristic vs. load current is then given by (Offset disabled):
Where R
LL
is the resulting load-line resistance implemented by the CORE Section.
The whole power supply can be then represented by a “real” voltage generator with an
equivalent output resistance R
LL
and a voltage value of VID.
R
FB
resistor can be then designed according to the R
LL
specifications as follow:
Caution:
Load-Line (DROOP) implementation is optional, in case it is not desired, the resulting cur-
rent information may be employed for other purposes, such as an additional Load Indicator
N
I
NB
Lx
CSx+
CSx-
DCR
x
R
C
R
G
R
ISEN
I
PHASEx
NB Current Sense across LS Mosfet
VDD Inductor DCR Current Sense
I
NB_ISEN
I
CSx-
=I
INFOx
From
ext Driver
V
OUT
V
CORE
VID
R
FB
I
DROOP
VID
R
FB
R
G
-------------
I
OUT
VID
R
LL
I
OUT
=
=
=
R
FB
R
LL
R
DCR
-------------
=
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