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參數(shù)資料
| 型號： | L6740LTR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Hybrid controller (4+1) for AMD SVID and PVID processors |
| 中文描述： | 混合控制器（4 1對AMD SVID和PVID）處理器 |
| 文件頁數(shù)： | 34/44頁 |
| 文件大小： | 657K |
| 代理商： | L6740LTR |
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Output voltage monitoring and protections
L6740L
34/44
Typical design considers the intervention of the Average OC before the per-phase OC, leav-
ing this last one as an extreme-protection in case of hardware failures in the external com-
ponents. Typical design flow is the following:
–
Define the maximum total output current (I
OC_AVGmax
) according to system
requirements
–
Set I
OC_TH
to 35
μ
A. This implies R
OC_TH
= 33k
(OC_PHASE pin is fixed to
1.24V and I
OC_TH
is the current programmed through R
OC_TH
).
–
Design R
G
resistor in order to have I
INFOx
= I
OC_TH
when I
OUT
is about 10% higher
than the I
OC_AVGmax
current. It results:
where N is the number of phases and DCR the DC resistance of the inductors. R
G
should be designed in worst-case conditions.
Design R
OC_AVG
in order to have the OC_AVG/LI pin voltage to V
OC_AVGTH
at the
desired maximum current I
OC_AVGmax
. It results:
–
where V
OC_AVGTH
is typically 2.5V and I
OC_AVGmax
is the AVG_OC threshold
desired.
Adjust the defined values according to bench-test of the application.
An additional capacitor in parallel to R
OC_AVG
can be considered to add a delay in
the protection intervention.
–
–
Note:
What previoulsy listed is the typical design flow. In any case, custom design may require
different settings and ratios between the per-phase OC threshold and the AVG OC
threshold. Applications with huge ripple across inductors may required to set I
OC_TH
to
values higher than 35
μ
A: in this case the threshold may be increased still keeping I
OC_TH
<
50
μ
A.
7.4.2
NB section
Since the NB Section reads the current across Low-Side MOSFET, it limits the bottom of the
NB inductor current entering in Constant Current until UV. In particular, since the device lim-
its the valley of the inductor current, the ripple entity, when not negligible, impacts on the real
OC threshold value and must be considered.
The device detects an Over Current condition when the current information I
ISEN
overcomes
the fixed threshold of I
OCTH_NB
(35
μ
A typ). When this happens, the device keeps the Low-
Side MOSFET on, also skipping clock cycles, until the threshold is crossed back and I
ISEN
results being lower than the I
OCTH_NB
threshold. After exiting the OC condition, the Low-
Side MOSFET is turned off and the High-Side is turned on with a duty cycle driven by the
PWM comparator.
The Section enters the Quasi-Constant-Current operation: the Low-Side MOSFET stays ON
until the current read becomes lower than I
OCP_NB
skipping clock cycles. The High-Side
MOSFET can be then turned ON with a T
ON
imposed by the control loop after the Low-Side
MOSFET turn-off and the Section works in the usual way until another OC event is detected.
This means that the average current delivered can slightly increase in Quasi-Constant-Cur-
R
G
1.1 I
N I
OCTH
-----------------------------------------------------------------
=
R
OC_AVG
V
R
I
OC_AVGmax
DCR
-----------------------------------------------
=
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