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參數(shù)資料
| 型號： | L6740LTR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Hybrid controller (4+1) for AMD SVID and PVID processors |
| 中文描述： | 混合控制器（4 1對AMD SVID和PVID）處理器 |
| 文件頁數(shù)： | 22/44頁 |
| 文件大?。?/td> | 657K |
| 代理商： | L6740LTR |
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Hybrid CPU support and CPU_TYPE detection
L6740L
22/44
Table 10.
PSI strategy
Figure 8.
System efficiency enhancement by PSI
5.4.4
HiZ management
L6740L is able to manage HiZ through both the PWMx and driver enable signals. When the
controller wants to set in high impedance the output of one Section, it set the relative PWM
floating and, at the same time, pulls-low the related ENDRV.
5.4.5
Hardware jumper override - V_FIX
Anytime the pin OVP/V_FIX is driven low, the controller enters V_FIX mode.
When in V_FIX mode, both NB and CORE Section voltages are governed by the information
shown in
Table 7
. Regardless of the state of PWROK, the device will work in SVI mode. SVC
and SVD are considered as static VID and the output voltage will change according to their
status. Dynamic SVC/SVD-change management is provided in this condition.
V_FIX mode is intended for system debug only.
Protection management differs in this case, see
Section 7.1
for details.
PSI_L
PSI strategy
GND
No Strategy.
PSI_L still reproduces the status of the PSI Flag
Pull-Up to <3V
Phase number is cut by 1 while PSI_L is asserted.
Pull-Up to 3.3V
Phase number is cut by 2 while PSI_L is asserted.
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