參數(shù)資料
型號(hào)： L6711TR
廠商： 意法半導(dǎo)體
英文描述： 3 PHASE CONTROLLER WITH DYNAMIC VID AND SELECTABLE DACs
中文描述： 3相控制器，動(dòng)態(tài)VID和可選數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù)： 31/38頁(yè)
文件大?。?/td> 591K
代理商： L6711TR
31/38
L6711
Figure 23. Equivalent Control Loop Gain Block Diagram (left) and Bode Diagram (right)
Compensation network can be simply designed placing
ω
Z
=
ω
LC
and imposing the cross-over frequency
ω
T
as desired obtaining:
V
IN
4
3
R
DROOP
18 LAYOUT GUIDELINES
Since the device manages control functions and high-current drivers, layout is one of the most important
things to consider when designing such high current applications.
A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing
radiation and a proper connection between signal and power ground can optimize the performance of the
control loops.
Integrated power drivers reduce components count and interconnections between control functions and
drivers, reducing the board space.
Here below are listed the main points to focus on when starting a new layout and rules are suggested for
a correct implementation.
18.1 Power Connections.
These are the connections where switching and continuous current flows from the input supply towards
the load. The first priority when placing components has to be reserved to this power section, minimizing
the length of each connection and loop as much as possible. To minimize noise and voltage spikes (EMI
and losses) these interconnections must be a part of a power plane and anyway realized by wide and thick
copper traces: loop must be anyway minimized. The critical components, i.e. the power transistors, must
be located as close as possible one to the other.
Figure 24 shows the details of the power connections involved and the current loops. The input capaci-
tance (C
IN
), or at least a portion of the total capacitance needed, has to be placed close to the power sec-
tion in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL
Rout
Cout
ESR
L/3
R
FB
R
F
C
F
REF
PWM
I
FB
V
COMP
V
OUT
d
V
IN
Z
F
dB
ω
ω
T
ω
Z
ω
LC
G
LOOP
Z
F
(s)
K
dB
FB
OSC
IN
R
V
V
K
=
1
5
4
R
F
----------------------------------
5
--
ω
T
ESR
+
(
)
-------------------------------------------------------
=
C
F
Co
L
3
--
R
F
-------------------
=
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