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參數(shù)資料
| 型號： | L6711TR |
| 廠商： | 意法半導體 |
| 英文描述： | 3 PHASE CONTROLLER WITH DYNAMIC VID AND SELECTABLE DACs |
| 中文描述： | 3相控制器，動態(tài)VID和可選數(shù)模轉換器 |
| 文件頁數(shù)： | 21/38頁 |
| 文件大?。?/td> | 591K |
| 代理商： | L6711TR |
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L6711
Overcoming the OC threshold during the dynamic VID causes the device to enter the constant current lim-
itation slowing down the output voltage dV/dt also causing the failure in the D-VID test.
The way in which the device modifies the reference depends on the VID_SEL status and then on the kind
of DAC selected.
9.1
Selecting the VRD10.x DAC, the device checks for VID code modifications on the rising edge of a clock
that is three times the switching frequency of each phase and waits for a confirmation on the following
falling edge. Once the new code is stable, on the next rising edge, the reference starts stepping up or down
in LSB increments (12.5mV) every clock cycle (still 3·F
SW
) until the new VID code is reached. During the
transition, VID code changes are ignored; the device re-starts monitoring VID after the transition has fin-
ished on the next rising edge available.
VID_SEL = OPEN (see Figure 14).
9.1.1 Warning:
if the new VID code is more than 1 LSB higher than the previous, the device will execute the transition
stepping the reference with a frequency equal to 3·F
SW
until the new code has reached: for this reason it
is recommended to carefully control the VID change rate in order to carefully control the slope of the output
voltage variation.
Figure 14. Dynamic VID Transition, VRD10.x DAC
Tsw/3
x 4 Step VID Transition
VRD10.x DAC
t
t
t
V
V
V
R
R
R
R
V
VID [0,5]
Int. Reference
Vout
Tsw
V
V
R
R
R
V
V
4 x 1 Step VID Transition - VRD10.x DAC
T
VID
V
V
V
V
V
V
V
V
R
V
V
V
V
V
V
t
VID Clock
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