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參數資料
| 型號： | L6711TR |
| 廠商： | 意法半導體 |
| 英文描述： | 3 PHASE CONTROLLER WITH DYNAMIC VID AND SELECTABLE DACs |
| 中文描述： | 3相控制器，動態(tài)VID和可選數模轉換器 |
| 文件頁數： | 16/38頁 |
| 文件大小： | 591K |
| 代理商： | L6711TR |
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L6711
16/38
6
The device embeds a selectable DAC that allows the output voltage to have a tolerance of ±0.5% (0.6%
for Hammer DAC) recovering from offsets and manufacturing variations. The VID_SEL pin selects the
DAC table used to program the reference for the regulation as shown in Table 7.
DAC SELECTION
Table 7. DAC Selection
VID pins are inputs of an internal DAC that is realized by means of a series of resistors providing a partition
of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise
point of the divider. The DAC output is delivered to an amplifier obtaining the voltage reference (i.e. the
set-point of the error amplifier, V
PROG
). Internal pull-ups are provided (realized with a 5
μ
A current gener-
ator up to 3V Typ); in this way, to program a logic "1" it is enough to leave the pin floating, while to program
a logic "0" it is enough to short the pin to SGND.
Programming the "11111x" code (NOCPU, VID5 is irrelevant), the device shuts down: all mosfets are
turned OFF and SS_END is shorted to SGND. Removing the code causes the device to restart.
The voltage identification (VID) pin configuration also sets the Over / Under Voltage protection (OVP/UVP)
thresholds.
7
The device embeds a Remote Sense Buffer to sense remotely the regulated voltage without any additional
external components. In this way, the output voltage programmed is regulated between the remote buffer
inputs compensating motherboard or connector losses. The very low-offset amplifier senses the output
voltage remotely through the pins FBR and FBG (FBR is for the regulated voltage sense while FBG is for
the ground sense) and reports this voltage internally at VSEN pin with unity gain eliminating the errors.
Keeping the FBR and FBG traces parallel and guarded by a power plane results in common mode cou-
pling for any picked-up noise.
If remote sense is not required, it is enough connecting the resistor R
FB
directly to the regulated voltage:
VSEN becomes not connected and still senses the output voltage through the remote buffer. In this case
the FBG and FBR pins must be connected anyway to the regulated voltage (See Figure 9).
REMOTE VOLTAGE SENSE
7.1
The remote buffer is included in the trimming chain in order to achieve ±0.5% accuracy (0.6% for the Ham-
mer DAC) on the output voltage when the RB is used: eliminating it from the control loop causes the reg-
ulation error to be increased by the RB offset worsening the device performances!
Warning:
VID_SEL
Selected DAC
OPEN
VRM / VRD 10.x DAC.
Output voltage ranges from 0.8185V to 1.5810V with 12.5mV steps (See Table 5).
Since the VIDx pins program the maximum output voltage, according to VRD 10.x specs, the device
automatically regulates with –19mV offset avoiding use of any external component to lower the
regulated voltage.
Since the -19mV offset is programmed during the production stage, no further error is introduced to
generate the offset since it is automatically recovered during the trimming stage.
VID5
OPEN
Output voltage ranges from 0.800V to 1.550V with 25mV steps (See Table 6).
Output voltage ranges from 0.825V to 1.575V with 25mV steps (See Table 6).
Since the +25mV offset is programmed during the production stage, no further error is
introduced to generate the offset since it is automatically recovered during the trimming
stage.
SGND
Hammer DAC
SGND
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