參數(shù)資料
型號(hào)： L6711TR
廠商： 意法半導(dǎo)體
英文描述： 3 PHASE CONTROLLER WITH DYNAMIC VID AND SELECTABLE DACs
中文描述： 3相控制器，動(dòng)態(tài)VID和可選數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù)： 29/38頁(yè)
文件大?。?/td> 591K
代理商： L6711TR
29/38
L6711
Figure 21. Controller Power Dissipated (Quiescent + Switching; V
CC
= V
CCDR
= V
BOOT
= 12V)
17 SYSTEM CONTROL LOOP COMPENSATION
The control loop is composed by the Current Sharing control loop and the Average Current Mode control
loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its
regulation: the Current Sharing control loop equalize the currents in the inductors while the Average Cur-
rent Mode control loop fixes the output voltage equal to the reference programmed by VID. Figure 22
shows the block diagram of the system control loop.
Figure 22. Main Control Loop Diagram
The average current mode control loop is reported in Figure 23. The current information I
FB
sourced by
the FB pin flows into R
FB
implementing the dependence of the output voltage from the read current.
The system can be modeled with an equivalent single phase converter which only difference is the equiv-
alent inductor L/3 (where each phase has an L inductor).The ACM control loop gain results (obtained
opening the loop after the COMP pin):
0
500
1000
1500
2000
2500
3000
100
300
500
700
900
Switching Frequency [kHz] per Phase
C
Q
G_HS
=24nC
Q
G_LS
=62nC
Q
G_HS
=18nC
Q
G_LS
=47nC
Q
G_HS
=36nC
Q
G_LS
=94nC
Q
G_HS
=48nC
Q
G_LS
=124nC
Q
G_HS
=72nC
Q
G_LS
=196nC
0
500
1000
1500
2000
2500
3000
100
300
500
700
900
Switching Frequency [kHz] per Phase
C
Q
G_HS
=24nC
Q
G_LS
=62nC
Q
G_HS
=18nC
Q
G_LS
=47nC
Q
G_HS
=36nC
Q
G_LS
=94nC
Q
G_HS
=48nC
Q
G_LS
=124nC
Q
G_HS
=72nC
Q
G_LS
=196nC
R
GATE
= R
GATE_MOSFET
= 0 R
GATE_HS
= 2.2
; R
GATE_LS
= 3.3
; · R
GATE_MOSFET
= 1
COMP
VID
FB
R
FB
4/5
Z
F
(s)
ERROR AMPLIFIER
PWM3
PWM1
CURRENT
SHARING
DUTY CYCLE
CORRECTION
Co
Ro
L3
L1
PWM2
L2
1/5
1/5
1/5
I
INFO1
I
INFO2
I
INFO3
I
FB
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