參數(shù)資料
型號(hào)： L6711TR
廠商： 意法半導(dǎo)體
英文描述： 3 PHASE CONTROLLER WITH DYNAMIC VID AND SELECTABLE DACs
中文描述： 3相控制器，動(dòng)態(tài)VID和可選數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù)： 15/38頁(yè)
文件大?。?/td> 591K
代理商： L6711TR
15/38
L6711
5.2
Shorting CS_SEL pin to SGND, the current flowing trough each phase is read using the voltage drop
across the output inductor or across a sense resistor (R
SENSE
) in its series and internally converted into a
current. The transconductance ratio is issued by the external resistor Rg placed outside the chip between
CSx- and CSx+ pins toward the reading points (see Figure 6 right).
The current sense circuit always tracks the current sensed and still sources a constant 50
μ
A current from
the CSx+ pin: this pin is used as a reference keeping the CSx- pin to this voltage. To correctly reproduce
the inductor current an R-C filtering network must be introduced in parallel to the sensing element.
The current that flows from the CSx- pin is then given by the following equation (See Figure 8):
+
=
INDUCTOR CURRENT READING
Where IP
HASEx
is the current carried by the relative phase.
Considering now to match the time constant between the inductor and the R-C filter applied (Time con-
stant mismatches cause the introduction of poles into the current reading network causing instability.
Moreover, it is also important for the load transient response and to let the system show resistive equiva-
lent output impedance), it results:
where
Where I
INFOx
is the current information reproduced internally.
50
μ
A offset allows negative current reading, enabling the device to check for dangerous returning current
between the phases assuring the complete current equalization. From the current information of each
phase, information about the total current delivered (I
DROOP
= I
INFO1
+I
INFO2
+ I
INFO3
) and the average cur-
rent for each phase (I
AVG
= (I
INFO1
+ I
INFO2
+ I
INFO3
)/3) is taken. I
INFOX
is then compared to I
AVG
to give the
correction to the PWM output in order to equalize the current carried by the three phases.
Since Rg is designed considering the OC protection, to allow further flexibility in the system design, the
resistor in series to CSx+ can be split in two resistors as shown in Figure 8.
Figure 8. Inductor Current Sense
I
CSx-
50
μ
A
R
L
R
g
------
1
s
R
------
+
1
s R
g RC
)
Cg
+
------------------------------------------------
I
PHASEx
R
L
------
R
g RC
)
Cg
I
CSx-
≥
50
μ
A
R
L
Rg
-------
I
PHASEx
+
50
μ
A
I
INFOx
+
=
=
=
I
INFOx
I
PHASEx
R
L
Rg
-------
=
L
R
L
R
g(RC)
C
g
Rg
CSx+
CSx-
PHASEx
OUT
I
PHASE
CS_SEL
R
g(a)
50
μ
A
I
CSx-
Design Equations:
R
g RC
)
R
L
C
g
------------------
=
R
g RC
)
R
g a
+
Rg
=
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