參數(shù)資料
型號(hào)： KSZ8851SNL-EVAL
廠商： Micrel Inc
文件頁數(shù)： 57/80頁
文件大?。?/td> 0K
描述： BOARD EVALUATION KSZ8851SNL
產(chǎn)品培訓(xùn)模塊： KSZ8851 10/100 Embedded Controllers
標(biāo)準(zhǔn)包裝： 1
系列： LinkMD®
主要目的： 接口，以太網(wǎng)控制器（PHY 和 MAC）
嵌入式： 否
已用 IC / 零件： KSZ8851SNL
主要屬性： 1 個(gè)端口，100BASE-TX/10BASE-T
次要屬性： SPI 接口，LinkMD 線纜診斷
已供物品： 板，文檔
產(chǎn)品目錄頁面： 1081 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： 576-3299-6-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
576-3299-1-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
576-3299-2-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
576-3254-ND - IC CTLR MAC/PHY NON-PCI 32-QFN
其它名稱： 576-3293
Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
60
M9999-083109-2.0
Bit
Default
R/W
Description
15-13
0x0
RW
Reserved.
12
0x0
RW
Read Enable
1 = Read cycle is enabled (MIB counter will clear after read).
0 = No operation.
11-10
0x0
RW
Table Select
00 = reserved.
01 = reserved.
10 = reserved.
11 = MIB counter selected.
9-5
-
RW
Reserved
4-0
0x00
RW
Indirect Address
Bit 4-0 of indirect address for 32 MIB counter locations.
0xCA – 0xCF: Reserved
Indirect Access Data Low Register (0xD0 – 0xD1): IADLR
This register contains the indirect data (low word) for MIB counter.
Bit
Default
R/W
Description
15-0
0x0000
RW
Indirect Low Word Data
Bit 15-0 of indirect data.
Indirect Access Data High Register (0xD2 – 0xD3): IADHR
This register contains the indirect data (high word) for MIB counter.
Bit
Default
R/W
Description
15-0
0x0000
RW
Indirect High Word Data
Bit 31-16 of indirect data.
Power Management Event Control Register (0xD4 – 0xD5): PMECR
This register is used to control the KSZ8851SNL power management event, capabilities and status.
Bit
Default Value
R/W
Description
15
-
RO
Reserved
14
0
RW
PME Delay Enable
This bit is used to enable the delay of PME output pin 2 assertion.
When this bit is set to 1, the device will not assert the PME output till the device’s all
clocks are running and ready for host access.
When this bit is set to 0, the device will assert the PME output without delay.
This bit is only valid when Auto Wake-Up Enable (bit7) is set to 1 in this register.
13
0
RW
Reserved
12
0
RW
PME Output Polarity
This bit is used to control the PME output pin 2 polarity.
When this bit is set to 1, the PME output pin 2 is active high.
When this bit is set to 0, the PME output pin 2 is active low.
11-8
0x0
RW
Wake-on-LAN to PME Output Enable
These four bits are used to enable the PME output pin 2 asserted when one of these
wake-on-LAN events is detected:
Bit 11: is corresponding to receive wake-up frame.
Bit 10: is corresponding to receive magic packet.
Bit 9: is corresponding to link change from down to up.
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