參數(shù)資料
型號: KSZ8851SNL-EVAL
廠商: Micrel Inc
文件頁數(shù): 55/80頁
文件大小: 0K
描述: BOARD EVALUATION KSZ8851SNL
產(chǎn)品培訓(xùn)模塊: KSZ8851 10/100 Embedded Controllers
標(biāo)準(zhǔn)包裝: 1
系列: LinkMD®
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8851SNL
主要屬性: 1 個端口,100BASE-TX/10BASE-T
次要屬性: SPI 接口,LinkMD 線纜診斷
已供物品: 板,文檔
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 576-3299-6-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
576-3299-1-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
576-3299-2-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
576-3254-ND - IC CTLR MAC/PHY NON-PCI 32-QFN
其它名稱: 576-3293
Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
59
M9999-083109-2.0
Flow Control High Watermark Register (0xB2 – 0xB3): FCHWR
This register is used to control the flow control for high watermark in QMU RX queue.
Bit
Default Value
R/W
Description
15-12
-
RW
Reserved
11-0
0x0300
RW
FCHWC Flow Control High Watermark Configuration
These bits are used to define the QMU RX queue high watermark configuration. It is in
double words count and default is 3.072 KByte available buffer space out of 12 KByte.
Flow Control Overrun Watermark Register (0xB4 – 0xB5): FCOWR
This register is used to control the flow control for overrun watermark in QMU RX queue
Bit
Default Value
R/W
Description
15-12
-
RW
Reserved
11-0
0x0040
RW
FCLWC Flow Control Overrun Watermark Configuration
These bits are used to define the QMU RX queue overrun watermark configuration. It is in
double words count and default is 256 Bytes available buffer space out of 12 Kbyte.
0xB6 – 0xBF: Reserved
Chip ID and Enable Register (0xC0 – 0xC1): CIDER
This register contains the chip ID and the chip enable bit.
Bit
Default
R/W
Description
15-8
0x88
RO
Family ID
Chip family ID
7-4
0x7
RO
Chip ID
0x7 is assigned to KSZ8851SNL
3-1
0x1
RO
Revision ID
0
0x0
RW
Reserved
0xC2 – 0xC5: Reserved
Chip Global Control Register (0xC6 – 0xC7): CGCR
This register contains the global control for the chip function.
Bit
Default
R/W
Description
15-12
0x0
RW
Reserved
11-10
0x2
RW
Reserved
9
0x0
RW
LEDSEL0
This bit sets the LEDSEL0 selection for LED1 and LED0.
PHY port LED indicators, defined as below:
LEDSEL0
0
1
LED1 (pin32)
100BT
ACT
LED0 (pin1)
LINK/ACT
LINK
8
0x0
R/W
Reserved
7-0
0x35
RW
Reserved
Indirect Access Control Register (0xC8 – 0xC9): IACR
This register contains the indirect control for the MIB counter (Write IACR triggers a command. Read access is
determined by bit 12).
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