參數(shù)資料
型號(hào)： KSZ8851SNL-EVAL
廠(chǎng)商： Micrel Inc
文件頁(yè)數(shù)： 37/80頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION KSZ8851SNL
產(chǎn)品培訓(xùn)模塊： KSZ8851 10/100 Embedded Controllers
標(biāo)準(zhǔn)包裝： 1
系列： LinkMD®
主要目的： 接口，以太網(wǎng)控制器（PHY 和 MAC）
嵌入式： 否
已用 IC / 零件： KSZ8851SNL
主要屬性： 1 個(gè)端口，100BASE-TX/10BASE-T
次要屬性： SPI 接口，LinkMD 線(xiàn)纜診斷
已供物品： 板，文檔
產(chǎn)品目錄頁(yè)面： 1081 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： 576-3299-6-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
576-3299-1-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
576-3299-2-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
576-3254-ND - IC CTLR MAC/PHY NON-PCI 32-QFN
其它名稱(chēng)： 576-3293
Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
42
M9999-083109-2.0
EEPROM Control Register (0x22 – 0x23): EEPCR
To support an external EEPROM, pulled-up the EED_IO pin to High; otherwise, it is pulled-down to Low. If an external
EEPROM is not used, the software programs the host MAC address. If an EEPROM is used in the design, the chip host
MAC address is loaded from the EEPROM immediately after reset. The KSZ8851SNL allows the software to access (read
and write) the EEPROM directly; that is, the EEPROM access timing can be fully controlled by the software if the
EEPROM Software Access bit is set.
Bit
Default Value
R/W
Description
15-6
-
RO
Reserved.
5
0
WO
EESRWA EEPROM Software Read or Write Access
0: software read enable to access EEPROM when software access enabled (bit 4 is “1”)
1: software write enable to access EEPROM when software access enabled (bit 4 is “1”).
4
0
RW
EESA EEPROM Software Access
1: enable software to access EEPROM through bit 3 to bit 0.
0: disable software to access EEPROM.
3
-
RO
EESB EEPROM Status Bit
Data Receive from EEPROM. This bit directly reads the EED_IO pin 6.
2-0
0x0
RW
EECB EEPROM Control Bits
Bit 2: Data Transmit to EEPROM. This bit directly controls the device’s EED_IO pin 6.
Bit 1: Serial Clock. This bit directly controls the device’s EESK pin 7.
Bit 0: Chip Select for EEPROM. This bit directly controls the device’s EECS pin 10.
Memory BIST Info Register (0x24 – 0x25): MBIR
This register indicates the build-in self test result for both TX and RX memories after power-up/reset.
Bit
Default Value
R/W
Description
15-13
0x0
RO
Reserved
12
-
RO
TXMBF TX Memory BIST Test Finish
When set, it indicates the Memory Built In Self Test completion for the TX Memory.
11
-
RO
TXMBFA TX Memory BIST Test Fail
When set, it indicates the TX Memory Built In Self Test has failed.
10-8
-
RO
TXMBFC TX Memory BIST Test Fail Count
To indicate the TX Memory Built In Self Test failed count
7-5
-
RO
Reserved
4
-
RO
RXMBF RX Memory Bist Finish
When set, it indicates the Memory Built In Self Test completion for the RX Memory.
3
-
RO
RXMBFA RX Memory Bist Fail
When set, it indicates the RX Memory Built In Self Test has failed.
2-0
-
RO
RXMBFC RX Memory BIST Test Fail Count
To indicate the RX Memory Built In Self Test failed count.
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