參數(shù)資料
型號(hào): KSZ8851SNL-EVAL
廠商: Micrel Inc
文件頁(yè)數(shù): 38/80頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION KSZ8851SNL
產(chǎn)品培訓(xùn)模塊: KSZ8851 10/100 Embedded Controllers
標(biāo)準(zhǔn)包裝: 1
系列: LinkMD®
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8851SNL
主要屬性: 1 個(gè)端口,100BASE-TX/10BASE-T
次要屬性: SPI 接口,LinkMD 線纜診斷
已供物品: 板,文檔
產(chǎn)品目錄頁(yè)面: 1081 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 576-3299-6-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
576-3299-1-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
576-3299-2-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
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其它名稱(chēng): 576-3293
Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
43
M9999-083109-2.0
Global Reset Register (0x26 – 0x27): GRR
This register controls the global and QMU reset functions with information programmed by the CPU.
Bit
Default Value
R/W
Description
15-2
0x0000
RO
Reserved
1
0
RW
QMU Module Soft Reset
1: Software reset is active to clear both TXQ and RXQ memories.
0: Software reset is inactive.
QMU software reset will flush out all TX/RX packet data inside the TXQ and RXQ
memories and reset all QMU registers to default value.
0
RW
Global Soft Reset
1: Software reset is active.
0: Software reset is inactive.
Global software reset will affect PHY, MAC, QMU, DMA, and the switch core, all registers
value are set to default value.
0x28 – 0x29: Reserved
Wakeup Frame Control Register (0x2A – 0x2B): WFCR
This register holds control information programmed by the CPU to control the wake up frame function.
Bit
Default Value
R/W
Description
15-8
0x00
RO
Reserved
7
0
RW
MPRXE
Magic Packet RX Enable
When set, it enables the magic packet pattern detection.
When reset, the magic packet pattern detection is disabled.
6-4
0x0
RO
Reserved
3
0
RW
WF3E
Wake up Frame 3 Enable
When set, it enables the Wake up frame 3 pattern detection.
When reset, the Wake up frame 3 pattern detection is disabled.
2
0
RW
WF2E
Wake up Frame 2 Enable
When set, it enables the Wake up frame 2 pattern detection.
When reset, the Wake up frame 2 pattern detection is disabled.
1
0
RW
WF1E
Wake up Frame 1 Enable
When set, it enables the Wake up frame 1 pattern detection.
When reset, the Wake up frame 1 pattern detection is disabled.
0
RW
WF0E
Wake up Frame 0 Enable
When set, it enables the Wake up frame 0 pattern detection.
When reset, the Wake up frame 0 pattern detection is disabled.
0x2C – 0x2F: Reserved
Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0
This register contains the expected CRC values of the Wake up frame 0 pattern.
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