參數(shù)資料
型號(hào)： KSZ8851SNL-EVAL
廠商： Micrel Inc
文件頁(yè)數(shù)： 46/80頁(yè)
文件大小： 0K
描述： BOARD EVALUATION KSZ8851SNL
產(chǎn)品培訓(xùn)模塊： KSZ8851 10/100 Embedded Controllers
標(biāo)準(zhǔn)包裝： 1
系列： LinkMD®
主要目的： 接口，以太網(wǎng)控制器（PHY 和 MAC）
嵌入式： 否
已用 IC / 零件： KSZ8851SNL
主要屬性： 1 個(gè)端口，100BASE-TX/10BASE-T
次要屬性： SPI 接口，LinkMD 線纜診斷
已供物品： 板，文檔
產(chǎn)品目錄頁(yè)面： 1081 (CN2011-ZH PDF)
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576-3299-1-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
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其它名稱(chēng)： 576-3293
Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
50
M9999-083109-2.0
Bit
Default Value
R/W
Description
6
0x0
RW
RXME Receive Multicast Enable
When this bit is set, the RX module receives all the multicast frames (including broadcast
frames).
5
0x0
RW
RXUE Receive Unicast Enable
When this bit is set, the RX module receives unicast frames that match the 48-bit Station
MAC address of the module.
4
0x0
RW
RXAE Receive All Enable
When this bit is set, the KSZ8851SNL receives all incoming frames, regardless of the
frame’s destination address (see Address Filtering Scheme in Table 3 for detail).
3
0x0
RW
Reserved
2
0x0
RW
Reserved
1
0x0
RW
RXINVF Receive Inverse Filtering
When this bit is set, the KSZ8851SNL receives function with address check operation in
inverse filtering mode (see Address Filtering Scheme in Table 3 for detail).
0
0x0
RW
RXE Receive Enable
When this bit is set, the RX block is enabled and placed in a running state.
When this bit is cleared, the receive process is placed in the stopped state upon
completing reception of the current frame.
Receive Control Register 2 (0x76 – 0x77): RXCR2
This register holds control information programmed by the CPU to control the receive function.
Bit
Default Value
R/W
Description
15-8
-
RO
Reserved
7-5
0x0
WO
SRDBL SPI Receive Data Burst Length
These three bits are used to define for SPI receive data burst length during DMA
operation from the host CPU to access RXQ frame buffer.
000: 4 Bytes data burst
001: 8 Bytes data burst
010: 16 Bytes data burst
011: 32 Bytes data burst
100: Single frame data burst
101-111: NA (reserved)
Note: It needs RXQ FIFO Read command byte before each data burst.
4
0x0
RW
IUFFP IPV4/IPV6/UDP Fragment Frame Pass
When this bit is set, the KSZ8851SNL will pass the checksum check at receive side for
IPv4/IPv6 UDP frame with fragment extension header.
When this bit is cleared, the KSZ8851SNL will perform checksum operation based on
configuration and doesn’t care whether it’s a fragment frame or not.
3
0x0
RW
RXIUFCEZ Receive IPV4/IPV6/UDP Frame Checksum Equal Zero
When this bit is set, the KSZ8851SNL will pass the filtering for Ipv4/IPV6 UDP frame with
UDP checksum equal to zero.
When this bit is cleared, the KSZ8851SNL will drop IPV4/IPV6 UDP packet with UDP
checksum equal to zero.
2
0x1
RW
UDPLFE UDP Lite Frame Enable
When this bit is set, the KSZ8851SNL will check the checksum at receive side and
generate the checksum at transmit side for UDP Lite frame.
When this bit is cleared, the KSZ8851SNL will pass the checksum check at receive side
and skip the checksum generation at transmit side for UDP Lite frame.
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