參數(shù)資料
型號(hào)： KSZ8851-32MQLI
廠商： Micrel Inc
文件頁(yè)數(shù)： 44/88頁(yè)
文件大?。?/td> 0K
描述： IC CTLR MAC/PHY NON PCI 128PQFP
標(biāo)準(zhǔn)包裝： 66
控制器類型： 以太網(wǎng)控制器，MAC/PHY
接口： 總線
電源電壓： 1.8V，2.5V，3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
其它名稱： 576-3630
KSZ8851-32MQLI-ND
Micrel, Inc.
KSZ8851-16/32 MQL/MQLI
August 2009
5
M9999-083109-2.0
Transmit Queue (TXQ) Frame Format ........................................................................................................................... 33
Frame Transmitting Path Operation in TXQ ................................................................................................................... 34
Driver Routine for Transmit Packet from Host Processor to KSZ8851M ....................................................................... 35
Receive Queue (RXQ) Frame Format............................................................................................................................ 38
Frame Receiving Path Operation in RXQ....................................................................................................................... 38
Driver Routine for Receive Packet from KSZ8851M to Host Processor ........................................................................ 39
EEPROM Interface............................................................................................................................................................... 40
Loopback Support........................................................................................................................................................... 41
Near-end (Remote) Loopback ........................................................................................................................................ 41
Far-end (Local) Loopback .............................................................................................................................................. 41
CPU Interface I/O Registers ............................................................................................................................................... 42
I/O Registers................................................................................................................................................................... 42
Internal I/O Registers Space Mapping............................................................................................................................ 43
Register Map: MAC, PHY and QMU................................................................................................................................... 49
Bit Type Definition........................................................................................................................................................... 49
0x00 – 0x05: Reserved................................................................................................................................................... 49
Bus Error Status Register (0x06 – 0x07): BESR ............................................................................................................ 49
Chip Configuration Register (0x08 – 0x09): CCR .......................................................................................................... 49
0x0A – 0x0F: Reserved .................................................................................................................................................. 50
Host MAC Address Registers: MARL, MARM and MARH ............................................................................................. 50
Host MAC Address Register Low (0x10 – 0x11): MARL................................................................................................ 50
Host MAC Address Register Middle (0x12 – 0x13): MARM........................................................................................... 50
Host MAC Address Register High (0x14 – 0x15): MARH .............................................................................................. 50
0x16 – 0x1F: Reserved .................................................................................................................................................. 51
On-Chip Bus Control Register (0x20 – 0x21): OBCR .................................................................................................... 51
EEPROM Control Register (0x22 – 0x23): EEPCR ....................................................................................................... 51
Memory BIST Info Register (0x24 – 0x25): MBIR .......................................................................................................... 52
Global Reset Register (0x26 – 0x27): GRR ................................................................................................................... 52
0x28 – 0x29: Reserved................................................................................................................................................... 52
Wakeup Frame Control Register (0x2A – 0x2B): WFCR ............................................................................................... 52
0x2C – 0x2F: Reserved .................................................................................................................................................. 53
Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0 ........................................................................................ 53
Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1 ........................................................................................ 53
Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0 ................................................................................ 53
Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1 ................................................................................ 54
Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2 ................................................................................ 54
Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3................................................................................ 54
0x3C – 0x3F: Reserved .................................................................................................................................................. 54
Wakeup Frame 1 CRC0 Register (0x40 – 0x41): WF1CRC0 ........................................................................................ 54
Wakeup Frame 1 CRC1 Register (0x42 – 0x43): WF1CRC1 ........................................................................................ 54
Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0 ................................................................................ 54
Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1 ................................................................................ 55
Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2 ................................................................................ 55
Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3................................................................................ 55
0x4C – 0x4F: Reserved .................................................................................................................................................. 55
Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0 ........................................................................................ 55
Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC1 ........................................................................................ 55
Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0 ................................................................................ 55
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