參數(shù)資料
型號(hào)： KSZ8851-32MQLI
廠商： Micrel Inc
文件頁數(shù)： 42/88頁
文件大?。?/td> 0K
描述： IC CTLR MAC/PHY NON PCI 128PQFP
標(biāo)準(zhǔn)包裝： 66
控制器類型： 以太網(wǎng)控制器，MAC/PHY
接口： 總線
電源電壓： 1.8V，2.5V，3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
其它名稱： 576-3630
KSZ8851-32MQLI-ND
PIC16F8X
DS30430C-page 48
1998 Microchip Technology Inc.
8.9
Interrupts
The PIC16F8X has 4 sources of interrupt:
External interrupt RB0/INT pin
TMR0 overflow interrupt
PORTB change interrupts (pins RB7:RB4)
Data EEPROM write complete interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also contains
the individual and global interrupt enable bits.
The global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. Bit GIE is cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine as well as sets the GIE bit, which
re-enable interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
When an interrupt is responded to; the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. For external interrupt events, such as the
RB0/INT pin or PORTB change interrupt, the interrupt
latency will be three to four instruction cycles. The
exact latency depends when the interrupt event occurs
(Figure 8-17). The latency is the same for both one and
two cycle instructions. Once in the interrupt service
routine the source(s) of the interrupt can be determined
by polling the interrupt flag bits. The interrupt flag bit(s)
must be cleared in software before re-enabling
interrupts to avoid infinite interrupt requests.
FIGURE 8-16: INTERRUPT LOGIC
Note 1: Individual interrupt flag bits are set
regardless
of
the
status
of
their
corresponding mask bit or the GIE bit.
RBIF
RBIE
T0IF
T0IE
INTF
INTE
GIE
EEIE
Wake-up
(If in SLEEP mode)
Interrupt to CPU
EEIF
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