- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374354 > KM416RD4C (SAMSUNG SEMICONDUCTOR CO. LTD.) Direct Rambus DRAM(Direct Rambus 動態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號： | KM416RD4C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Direct Rambus DRAM(Direct Rambus 動態(tài)RAM) |
| 中文描述： | 直接Rambus公司的DRAM（動態(tài)內(nèi)存直接Rambus公司） |
| 文件頁數(shù)： | 6/59頁 |
| 文件大?。?/td> | 4654K |
| 代理商： | KM416RD4C |
第1頁第2頁第3頁第4頁第5頁當前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁
Page 7
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.2 September 1998
TARGET
Packet Format
Figure Figure shows the formats of the ROWA and ROWR
packets on the ROW pins. Table Table describes the fields
which comprise these packets. DR4T and DR4F bits are
encoded to contain both the DR4 device address bit and a
framing bit which allows the ROWA or ROWR packet to be
recognized by the RDRAM.
The AV (ROWA/ROWR packet selection) bit distinguishes
between the two packet types. Both the ROWA and ROWR
packet provide a five bit device address and a four bit bank
address. An ROWA packet uses the remaining bits to specify
a nine bit row address, and the ROWR packet uses the
remaining bits for an eleven bit opcode field. Note the use of
the “RsvX” notation to reserve bits for future address field
extension.
Figure 3 also shows the formats of the COLC, COLM, and
COLX packets on the COL pins. Table Table describes the
fields which comprise these packets.
The COLC packet uses the S (Start) bit for framing. A
COLM or COLX packet is aligned with this COLC packet,
and is also framed by the S bit.
The 23 bit COLC packet has a five bit device address, a four
bit bank address, a six bit column address, and a four bit
opcode. The COLC packet specifies a read or write
command, as well as some power management commands.
The remaining 17 bits are interpreted as a COLM (M=1) or
COLX (M=0) packet. A COLM packet is used for a COLC
write command which needs bytemask control. The COLM
packet is associated with the COLC packet from a time t
RTR
earlier. An COLX packet may be used to specify an indepen-
dent precharge command. It contains a five bit device
address, a four bit bank address, and a five bit opcode. The
COLX packet may also be used to specify some house-
keeping and power management commands. The COLX
packet is framed within a COLC packet but is not otherwise
associated with any other packet.
Table 4 : Field Description for ROWA Packet and ROWR Packet
Field
Description
DR4T,DR4F
Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit.
DR3..DR0
Device address for ROWA or ROWR packet.
BR3..BR0
Bank address for ROWA or ROWR packet. RsvB denotes bits reserved for future address extension.
AV
Selects between ROWA packet (AV=1) and ROWR packet (AV=0).
R8..R0
Row address for ROWA packet. RsvR denotes bits reserved for future row address extension.
ROP10..ROP0
Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions.
Table 5 : Field Description for COLC Packet, COLM Packet, and COLX Packet
Field
Description
S
Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets.
DC4..DC0
Device address for COLC packet.
BC3..BC0
Bank address for COLC packet. RsvB denotes bits reserved for future bank address extension.
C5..C0
Column address for COLC packet. RsvC denotes bits reserved for future column address extension.
COP3..COP0
Opcode field for COLC packet. Specifies read, write, precharge, and power management functions.
M
Selects between COLM packet (M=1) and COLX packet (M=0).
MA7..MA0
Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA8..0.
MB7..MB0
Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB8..0.
DX4..DX0
Device address for COLX packet.
BX3..BX0
Bank address for COLX packet. RsvB denotes bits reserved for future bank address extension.
XOP4..XOP0
Opcode field for COLX packet. Specifies precharge, I
OL
control, and power management functions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KM416S1021CT-G7 | 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface |
| KM416S1021CT-G8 | 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface |
| KM416S1021CT-GS | 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface |
| KM416S1120D | 512K x 16bit x 2 Banks Synchronous DRAM LVTTL |
| KM416S16230A | 4M x 16Bit x 4 Banks Synchronous DRAM(4M x 16位 x4組同步動態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM416RD4D | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD8AC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD8AC(D)-RK70 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD8AC(D)-RK80 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD8AC(DB)-RCG60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。